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6 commits

Author SHA1 Message Date
Thierry Reding
0ac7facb70 drm/nouveau/fault: Add support for GP10B
There is no BAR2 on GP10B and there is no need to map through BAR2
because all memory is shared between the GPU and the CPU. Add a custom
implementation of the fault sub-device that uses nvkm_memory_addr()
instead of nvkm_memory_bar2() to return the address of a pinned fault
buffer.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15 10:49:58 +10:00
Ben Skeggs
13e9572906 drm/nouveau/fault/gp100: expose MaxwellFaultBufferA
This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20 09:00:00 +10:00
Ben Skeggs
3968d6920b drm/nouveau/fault: add explicit control over fault buffer interrupts
The GPU will continually fire interrupts while a fault buffer GET != PUT,
and to stop the spurious interrupts while the handler does its thing, we
were disabling the fault buffer temporarily.

This is not actually a great idea to begin with, and made worse by Volta
resetting GET/PUT when it's reactivated.  So, let's not do that.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:46 +10:00
Ben Skeggs
809724560f drm/nouveau/fault: store get/put pri address in nvkm_fault_buffer
Will allow more shared fault buffer handling code between Pascal/Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:46 +10:00
Ben Skeggs
4d326469d9 drm/nouveau/fault: remove manual mapping of fault buffers into BAR2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:46 +10:00
Ben Skeggs
d0e9351e42 drm/nouveau/fault/gp100: implement replayable fault buffer initialisation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00