This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).
Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>