This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X.
Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B),
this patch names them as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many NOGP definitions. But these are not
used, and they are different from original usage. This patch removes
them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1. But we should use 0 for all cases in
reality. New Datasheet should be updated.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.
This patch was created based on the Rev.0.51 datasheet.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the
r8a779g0 subdriver.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.
Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function. They all fall back to the AXP221 compatible
string, so only that one needs to be listed in the driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220621034224.38995-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the compilation error, caused by updating constant variable.
Hence remove redundant constant variable, which is no more useful
as per new design.
The issue is due to some unstaged changes. Fix it up.
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
To act as an interrupt controller, a gpio bank relies on the
"interrupt-parent" of the pin controller.
When this optional "interrupt-parent" misses, do not create any IRQ domain.
This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when
the interrupt-parent = <exti> property is not declared in the Device Tree.
Fixes: 0eb9f68333 ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Samsung SoC pin controller driver uses only three defines from the
bindings header with pin configuration register values, which proves
the point that this header is not a proper bindings-type abstraction
layer with IDs.
Define the needed register values directly in the driver and stop using
the bindings header.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220605160508.134075-8-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20220624081022.32384-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On i.MX93, the pin mux reg offset is from 0x0,
so need to add the 'ZERO_OFFSET_VALID' flag to make
sure the pin at mux offset 0 can be found.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Link: https://lore.kernel.org/r/20220613031854.1571357-1-ping.bai@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the driver to use an immutable IRQ chip to fix this warning:
"not an immutable chip, please consider fixing it!"
Preserve per-chip labels by adding an ->irq_print_chip() callback.
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the below kernel-doc warning by adding the description for return
value.
"warning: No description found for return value of
'zynqmp_pmux_get_function_groups'".
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. As part of the output-enable configuration, ZynqMP pinctrl
driver takes care of removing the pins from tri-state.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
Previous implementation used absolute pin numbering and it was incorrect
for R_PIO pinctrl.
It's necessary to take into account the base pin number.
Fixes: 90be64e276 ("pinctrl: sunxi: implement pin_config_set")
Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The idea was right but the code was breaking in next.
I assume some unstaged commit was involed. Fix it up.
Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Fix reporting of input disabled pins on RZ/G2L.
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Merge tag 'renesas-pinctrl-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.20
- Fix reporting of input disabled pins on RZ/G2L.
After applying patches I get these warnings:
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1302:56:
warning: "/*" within comment [-Wcomment]
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1362:56:
warning: "/*" within comment [-Wcomment]
Something is wrong with the missing end-slashes. Add them.
Cc: Guodong Liu <guodong.liu@mediatek.com>
Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove pin definitions that do not support the R0 & R1 pinconfig property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-6-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Function bias_combo getter/setters already handle all cases advanced drive
configuration, include drive for I2C related pins.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-5-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1. I2C pins's resistance value can be controlled by rsel register.
This patch provides rsel (resistance selection) setting on mt8192.
2. Also add the missing pull type array for mt8192 to document the
pull type of each pin and prevent invalid pull type settings.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-4-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch provides the advanced drive raw data setting version
for I2C used pins on mt8192.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-3-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1. The dt-binding expects that drive-strength arguments be passed
in mA, but the driver was expecting raw values. And that this
commit changes the driver so that it is aligned with the binding.
2. This commit provides generic driving setup, which support
2/4/6/8/10/12/14/16mA driving, original driver just set raw data
setup setting when use drive-strength property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-2-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips. The bcm2835 pinctrl is also affected by this
warning.
Fix this by making the irqchip in the bcm2835 pinctrl driver immutable.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220614202831.236341-3-stefan.wahren@i2se.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The commit b8a19382ac ("pinctrl: bcm2835: Fix support for threaded level
triggered IRQs") assigned the irq_mask/unmask callbacks with the
already existing functions for irq_enable/disable. The wasn't completely
the right way (tm) to fix the issue, because these callbacks shouldn't
be identical. So fix this by rename the functions to represent their
intension and drop the unnecessary irq_enable/disable assigment.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220614202831.236341-2-stefan.wahren@i2se.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the
function was never assigned to the pingroup (even though the function
exists already).
Add this mode to the related pins.
Fixes: 5373a2c5ab ("pinctrl: qcom: Add msm8916 pinctrl driver")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update lpass lpi pin control driver, with clock optional check for ADSP
disabled platforms. This check required for distingushing ADSP based
platforms and ADSP bypass platforms.
In case of ADSP enabled platforms, where audio is routed through ADSP
macro and decodec GDSC Switches are triggered as clocks by pinctrl
driver and ADSP firmware controls them. So It's mandatory to enable
them in ADSP based solutions.
In case of ADSP bypass platforms clock voting is optional as these macro
and dcodec GDSC switches are maintained as power domains and operated from
lpass clock drivers.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1654921357-16400-3-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are no more used members in the struct intel_pingroup, drop them.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
