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12 commits

Author SHA1 Message Date
Alex Deucher
1b51916b97 drm/amdgpu: add VCN 3.0 AV1 registers 
This adds the AV1 registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 23:05:57 -04:00
Leo Liu
a5a2597771 drm/amdgpu: add VCN3.0 register headers (v2) 
Sienna_Cichlid VCN headers

v2: squash in updates (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:55 -04:00
Jane Jian
6aec5bb489 drm/amdgpu: add VCN0 and VCN1 needed headers 
Add mmsch part registers

Signed-off-by: Jane Jian <jane.jian@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-25 16:50:09 -04:00
Leo Liu
c54a60db0d drm/amdgpu: add VCN2.5 headers 
VCN is the multi-media block.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Hawking Zhang
326354fa97 drm/amdgpu: add VCN 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:33 -05:00
Tom St Denis
054d282d17 drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers 
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-03-19 15:36:48 -05:00
James Zhu
b53d3049d2 drm/amdgpu/vcn:Add new register offset/mask for VCN 
Add new register offset/mask for VCN to support
latest VCN implementation.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-12 12:53:52 -05:00
James Zhu
b604545b92 drm/amdgpu:Add new register offset/mask to support VCN DPG mode 
New register offset/mask need to be added to support VCN DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:23 -05:00
Boyuan Zhang
44287b7190 drm/amdgpu: add system interrupt mask for jrbc 
Add new mask for enabling system interrupt for jrbc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-08-27 11:10:10 -05:00
Boyuan Zhang
8709890892 drm/amdgpu: add system interrupt register offset header 
Add new register offset for enabling system interrupt.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-08-27 11:10:09 -05:00
Boyuan Zhang
50613395ab drm/amdgpu: add more jpeg register offset headers 
Add more jpeg registers defines that are needed for jpeg ring functions

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:35 -05:00
Feifei Xu
b1ebd7c0cd drm/amd/include:cleanup raven1 vcn header files. 
Cleanup asic_reg/raven1/VCN folder. Remove unused vcn_1_0_default.h.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-06 12:48:26 -05:00