4 commits

Author	SHA1	Message	Date
Carlos Bilbao	75a616168b	iommu/amd: Update copyright notice ... The most recent changes to AMD'S IOMMU, such as level 5 guest page table support date to the year 2023. Update copyright statement accordingly. Signed-off-by: Carlos Bilbao <carlos.bilbao@amd.com> Link: https://lore.kernel.org/r/20230420173006.3100682-1-carlos.bilbao@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>	2023-05-22 17:20:50 +02:00
Vasant Hegde	f594496403	iommu/amd: Add 5 level guest page table support ... Newer AMD IOMMU supports 5 level guest page table (v2 page table). If both processor and IOMMU supports 5 level page table then enable it. Otherwise fall back to 4 level page table. Co-developed-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Huang <wei.huang2@amd.com> Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Link: https://lore.kernel.org/r/20230310090000.1117786-1-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>	2023-03-28 15:31:31 +02:00
Vasant Hegde	0d571dcbe7	iommu/amd: Allocate page table using numa locality info ... Introduce 'struct protection_domain->nid' variable. It will contain IOMMU NUMA node ID. And allocate page table pages using IOMMU numa locality info. This optimizes page table walk by IOMMU. Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Link: https://lore.kernel.org/r/20230321092348.6127-2-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>	2023-03-22 15:43:39 +01:00
Vasant Hegde	aaac38f614	iommu/amd: Initial support for AMD IOMMU v2 page table ... Introduce IO page table framework support for AMD IOMMU v2 page table. This patch implements 4 level page table within iommu amd driver and supports 4K/2M/1G page sizes. Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Link: https://lore.kernel.org/r/20220825063939.8360-7-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>	2022-09-07 16:12:35 +02:00