Latest drivers version requires phy-mode to be set. Otherwise we will
use "NA" mode and the switch driver will invalidate this port mode.
Fixes: 65ac79e181 ("net: dsa: microchip: add the phylink get_caps")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.kernel.org/r/20220610081621.584393-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for the
USB core, but there are the usual "hot spots" of development activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes. It seems this driver will never
be finished given that the IP core is showing up in zillions
of new devices and each implementation decides to do something
different with it...
- uvc gadget driver updates as more devices start to use and
rely on this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for
the USB core, but there are the usual "hot spots" of development
activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes.
It seems this driver will never be finished given that the IP core
is showing up in zillions of new devices and each implementation
decides to do something different with it...
- uvc gadget driver updates as more devices start to use and rely on
this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems"
* tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits)
USB: new quirk for Dell Gen 2 devices
usb: dwc3: core: Add error log when core soft reset failed
usb: dwc3: gadget: Move null pinter check to proper place
usb: hub: Simplify error and success path in port_over_current_notify
usb: cdns3: allocate TX FIFO size according to composite EP number
usb: dwc3: Fix ep0 handling when getting reset while doing control transfer
usb: Probe EHCI, OHCI controllers asynchronously
usb: isp1760: Fix out-of-bounds array access
xhci: Don't defer primary roothub registration if there is only one roothub
USB: serial: option: add Quectel BG95 modem
USB: serial: pl2303: fix type detection for odd device
xhci: Allow host runtime PM as default for Intel Alder Lake N xHCI
xhci: Remove quirk for over 10 year old evaluation hardware
xhci: prevent U2 link power state if Intel tier policy prevented U1
xhci: use generic command timer for stop endpoint commands.
usb: host: xhci-plat: omit shared hcd if either root hub has no ports
usb: host: xhci-plat: prepare operation w/o shared hcd
usb: host: xhci-plat: create shared hcd after having added main hcd
xhci: prepare for operation w/o shared hcd
xhci: factor out parts of xhci_gen_setup()
...
Add clocks and clock-names to the rk3228 cru node, because
the device has to have at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220330121923.24240-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clocks and clock-names to the rk3036 cru node, because
the device has to have at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220330114847.18633-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clocks property to rk3066a/rk3188 cru node to fix warnings like:
'clocks' is a dependency of 'assigned-clocks'
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220329111323.3569-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clocks property to rk3288 cru node to fix warnings like:
'clocks' is a dependency of 'assigned-clocks'.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220329113657.4567-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The "amba" bus nodes wrapping all the DMA-330 nodes serve no useful
purpose, and certainly bear no relation at all to the actual underlying
interconnect topology. They appear to be cargo-cult copying from a
design misstep in the very early days of FDT adoption on ARM, which was
righted with the "arm,primecell" compatible, and the last trace of the
idea finally purged by commit 2ef7d5f342 ("ARM, ARM64: dts: drop
"arm,amba-bus" in favor of "simple-bus"").
As such, they can simply be removed and the DMA-330 nodes fitted into
the normal sort order.
The node names should be generic, so rename it to "dma-controller".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220330131608.30040-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add clocks and clock-names to the rv1108 cru node, because
the device has to have at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20220330131608.30040-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The '#dma-channels' property was deprecated in favor of one defined by
generic dma-common DT bindings. Add new property while keeping old one
for backwards compatibility.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220516142857.6419-3-krzysztof.kozlowski@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The '#dma-channels' and '#dma-requests' properties were deprecated in
favor of these defined by generic dma-common DT bindings. Add new
properties while keeping old ones for backwards compatibility.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220516142857.6419-2-krzysztof.kozlowski@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Patch series from Nick Hawkins:
"The GXP is the HPE BMC SoC that is used in the majority of HPE current
generation servers. Traditionally the asic will last multiple
generations of server before being replaced.
Info about SoC:
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
A9 core. It is capable of using an AXI bus to which a memory controller
is attached. It has multiple SPI interfaces to connect boot flash and
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has
multiple i2c engines to drive connectivity with a host infrastructure.
The initial patches enable the watchdog and timer enabling the host to
be able to boot."
* hpe/gxp-soc:
MAINTAINERS: Introduce HPE GXP Architecture
ARM: dts: Introduce HPE GXP Device tree
dt-bindings: arm: hpe: add GXP Support
dt-bindings: timer: hpe,gxp-timer: Add HPE GXP Timer and Watchdog
clocksource/drivers/timer-gxp: Add HPE GXP Timer
watchdog: hpe-wdt: Introduce HPE GXP Watchdog
ARM: configs: multi_v7_defconfig: Add HPE GXP ARCH
ARM: hpe: Introduce the HPE GXP architecture
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There are 40 branches this time, adding a lot of new hardware
support, and cleanups. Krzysztof Kozlowski continues his treewide
cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L
general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for designing
custom SoCs, the support for now is for the Fixed Virtual Platform
emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used
in upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly
for 32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based
IOT board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch,
a Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568
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Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"There are 40 branches this time, adding a lot of new hardware support,
and cleanups. Krzysztof Kozlowski continues his treewide cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the
RZ/G2L general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for
designing custom SoCs, the support for now is for the Fixed Virtual
Platform emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in
upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly for
32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based IOT
board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch, a
Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568"
* tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits)
ARM: dts: kswitch-d10: enable networking
ARM: dts: lan966x: add switch node
ARM: dts: lan966x: add serdes node
ARM: dts: lan966x: add reset switch reset node
ARM: dts: lan966x: add MIIM nodes
ARM: dts: lan966x: add hwmon node
ARM: dts: lan966x: add basic Kontron KSwitch D10 support
ARM: dts: lan966x: add flexcom I2C nodes
ARM: dts: lan966x: add flexcom SPI nodes
ARM: dts: lan966x: add all flexcom usart nodes
ARM: dts: lan966x: add missing uart DMA channel
ARM: dts: lan966x: add sgpio node
ARM: dts: lan966x: swap dma channels for crypto node
ARM: dts: lan966x: rename pinctrl nodes
ARM: dts: at91: sama7g5: remove interrupt-parent from gic node
ARM: dts: at91: use generic node name for dataflash
ARM: dts: turris-omnia: Add atsha204a node
arm64: dts: mt8192: Follow binding order for SCP registers
arm64: dts: mediatek: add mtk-snfi for mt7622
arm64: dts: mediatek: mt8195-demo: enable uart1
...
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220302024930.18758-3-tommy_huang@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220302024930.18758-2-tommy_huang@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
The IBM Everest and Rainier systems have a GPIO line that goes to the
power supplies. It has a dual function: 1) Fans Full Speed, and 2) Sync
input history.
Signed-off-by: Brandon Wyman <bjwyman@gmail.com>
Link: https://lore.kernel.org/r/20220421213638.1151193-1-bjwyman@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add initial version of device tree for Nuvia DC-SCM BMC which is
equipped with Aspeed AST2600 BMC SoC.
Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Link: https://lore.kernel.org/r/20220325190247.468079-1-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
set number of sample averaging to 128 for both PWR_AVG and VI_AVG
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220418094827.6185-1-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add eeprom (24c26) on each sled for storing sled fru information.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-7-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add an ioexp node on each sled baseed on DVT schematic, address at 0x41.
P0: SLEDX_SWD_MUX
P1: SLEDX_XRES_SWD_N
P2: SLEDX_CLKREQ_N
P3: SLEDX_PCIE_PWR_EN
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-6-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Update GPIO line names based on DVT schematic
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-5-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable mdio0 bus based on DVT schematic.
TODO: Add Marvell 88E6191 Switch
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-4-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Due to DVT schematic has stable spi signal, switch back to aspeed-smc
driver for improving performance.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-3-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable ehci0 node for USB2 host feature
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220509151118.4899-2-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Set "spi-max-frequency" to 50 MHz for all the flashes under the FMC
controller to ensure the clock frequency is calculated correctly.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Tao Ren <rentao.bupt@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220509175616.1089346-11-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
All these controllers support at least Dual SPI. Update the DTs.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220509175616.1089346-10-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
This is compatible with the current driver and addresses issues when
running 'make dt_binding_check'.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220509175616.1089346-2-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
Since SoM revision 1.9 the PHY has been replaced with an ADIN1300,
add an entry for it next to the original.
As Russell King pointed out, additional phy nodes cause warnings like:
mdio_bus 2188000.ethernet-1: MDIO device at address 1 is missing
To avoid this the new node has its status set to disabled. U-Boot will
be modified to enable the appropriate phy node after probing.
The existing ar8035 nodes have to stay enabled by default to avoid
breaking existing systems when they update Linux only.
Co-developed-by: Alvaro Karsz <alvaro.karsz@solid-run.com>
Signed-off-by: Alvaro Karsz <alvaro.karsz@solid-run.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.
The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
SAMA7G5-EK has 4 PDM microphones connected to PDMC0. PDMC0 pinmux is in
conflict with gmac1, gmac1 being enabled by default.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/all/20220307122202.2251639-6-codrin.ciubotariu@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Microchip's SAMA7G5 embeds two PDMCs. The PDMCs can be used to connect 2x4
PDM microphones.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/all/20220307122202.2251639-5-codrin.ciubotariu@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
As the DT specification recommends, the node names should be of a
generic nature. Thus, the most appropriate generic node name for
the at91 rtt IPs is the "rtc" node name.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/all/20220304161159.147784-3-sergiu.moga@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the required 'atmel,rtt-rtc-time-reg' property to the "rtt" nodes
of the board files that were missing it.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/all/20220304161159.147784-2-sergiu.moga@microchip.com
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Merge tag 'v5.18-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
Delete no longer needed properties of MediaTek Larbs for MT2701.
* tag 'v5.18-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm: dts: mediatek: Get rid of mediatek, larb for MM nodes
Link: https://lore.kernel.org/r/b4383f23-0adc-b9de-a1d9-abd1c2f82b27@gmail.com
This concludes a cleanup that was started back in 2019, with an
incompatible DT binding change. Kernels before 5.18 can no longer
use the updated dtb from 5.19, and the drivers no longer parse the
old properties, which breaks compatibility with older dtb files.
Link: https://lore.kernel.org/lkml/1546318276-18993-2-git-send-email-yong.wu@mediatek.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable all the necessary network related nodes, wire the pinctrl
configurations, add the PHYs and connect them to the corresponding
network ports.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-14-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the switch node and its 8 children ports. All are disabled by default.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-13-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the SerDes node. On the LAN966x SoC these SerDes are used to connect
network PHYs.
By default, that node is disabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-12-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the switch reset node which will later be used by the switch driver.
The switch reset also resets the GPIO controller and the SGPIO
controller, thus it also has to be connectected to these nodes. This way
the reset will only issued once for the first device requesting the
reset.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-11-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the MDIO controller nodes. The integrated PHYs are connected to the
second controller. This controller also takes care of the resets of the
integrated PHYs, thus it has two memory regions. The first controller
is routed to the external MDIO/MDC pins.
By default, they are disabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the monitoring node which covers the temperature sensor as well as
the PWM controller and the FAN tacho input.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-9-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
