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Author SHA1 Message Date
Liang He
89ab396d71 clk: meson: Hold reference returned by of_get_parent()
We should hold the reference returned by of_get_parent() and use it
to call of_node_put() for refcount balance.

Fixes: 88e2da8124 ("clk: meson: aoclk: refactor common code into dedicated file")
Fixes: 6682bd4d44 ("clk: meson: factorise meson64 peripheral clock controller drivers")
Fixes: bb6eddd1d2 ("clk: meson: meson8b: use the HHI syscon if available")

Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220628141038.168383-1-windhl@126.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-08-19 14:29:00 -07:00
Kevin Hilman
20425f6319 clk: meson: enable building as modules
Make it possible to build all clk drivers as modules, but default
remains built-in.

No functional changes.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com
2020-11-23 09:08:23 +01:00
Alexandre Mergnat
b11cfaba5b clk: meson: remove ee input bypass clocks
During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of this method are the duplicated clocks, means more string
comparison.

Specify parent directly with device-tree clock name.

Remove the bypass clock registration from the ee probe function.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:49 +02:00
Jerome Brunet
19a18d42bf clk: meson: eeclk: add init regs
Like the PLL and MPLL, the controller may require some magic setting to
be applied on startup.

This is needed when the initial setting is not applied by the boot ROM.
The controller need to do it when the setting applies to several clock,
like all the MPLLs in the case of g12a.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20 12:20:16 +02:00
Jerome Brunet
6682bd4d44 clk: meson: factorise meson64 peripheral clock controller drivers
The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those controllers so
it is time to factorize things a bit.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-04 09:52:11 +01:00