837d542a09
Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
760 lines
20 KiB
C
760 lines
20 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU75_H
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#define SMU75_H
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#pragma pack(push, 1)
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typedef struct {
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uint32_t high;
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uint32_t low;
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} data_64_t;
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typedef struct {
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data_64_t high;
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data_64_t low;
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} data_128_t;
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#define SMU__DGPU_ONLY
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 4
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
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#define SMU75_MAX_LEVELS_VDDC 16
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#define SMU75_MAX_LEVELS_VDDGFX 16
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#define SMU75_MAX_LEVELS_VDDCI 8
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#define SMU75_MAX_LEVELS_MVDD 4
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#define SMU_MAX_SMIO_LEVELS 4
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#define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
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#define SMU75_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
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#define SMU75_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS
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#define SMU75_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
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#define SMU75_MAX_LEVELS_UVD 8
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#define SMU75_MAX_LEVELS_VCE 8
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#define SMU75_MAX_LEVELS_ACP 8
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#define SMU75_MAX_LEVELS_SAMU 8
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#define SMU75_MAX_ENTRIES_SMIO 32
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#define DPM_NO_LIMIT 0
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#define DPM_NO_UP 1
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#define DPM_GO_DOWN 2
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#define DPM_GO_UP 3
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#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
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#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
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#define GPIO_CLAMP_MODE_VRHOT 1
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#define GPIO_CLAMP_MODE_THERM 2
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#define GPIO_CLAMP_MODE_DC 4
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#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
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#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
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#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
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#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
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#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
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#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
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#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
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#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
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#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
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#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
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#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
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#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
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#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
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#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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/* Virtualization Defines */
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#define CG_XDMA_MASK 0x1
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#define CG_XDMA_SHIFT 0
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#define CG_UVD_MASK 0x2
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#define CG_UVD_SHIFT 1
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#define CG_VCE_MASK 0x4
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#define CG_VCE_SHIFT 2
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#define CG_SAMU_MASK 0x8
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#define CG_SAMU_SHIFT 3
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#define CG_GFX_MASK 0x10
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#define CG_GFX_SHIFT 4
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#define CG_SDMA_MASK 0x20
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#define CG_SDMA_SHIFT 5
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#define CG_HDP_MASK 0x40
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#define CG_HDP_SHIFT 6
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#define CG_MC_MASK 0x80
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#define CG_MC_SHIFT 7
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#define CG_DRM_MASK 0x100
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#define CG_DRM_SHIFT 8
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#define CG_ROM_MASK 0x200
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#define CG_ROM_SHIFT 9
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#define CG_BIF_MASK 0x400
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#define CG_BIF_SHIFT 10
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#if defined SMU__DGPU_ONLY
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#define SMU75_DTE_ITERATIONS 5
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#define SMU75_DTE_SOURCES 3
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#define SMU75_DTE_SINKS 1
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#define SMU75_NUM_CPU_TES 0
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#define SMU75_NUM_GPU_TES 1
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#define SMU75_NUM_NON_TES 2
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#define SMU75_DTE_FAN_SCALAR_MIN 0x100
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#define SMU75_DTE_FAN_SCALAR_MAX 0x166
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#define SMU75_DTE_FAN_TEMP_MAX 93
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#define SMU75_DTE_FAN_TEMP_MIN 83
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#endif
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#define SMU75_THERMAL_INPUT_LOOP_COUNT 2
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#define SMU75_THERMAL_CLAMP_MODE_COUNT 2
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#define EXP_M1_1 93
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#define EXP_M2_1 195759
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#define EXP_B_1 111176531
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#define EXP_M1_2 67
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#define EXP_M2_2 153720
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#define EXP_B_2 94415767
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#define EXP_M1_3 48
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#define EXP_M2_3 119796
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#define EXP_B_3 79195279
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#define EXP_M1_4 550
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#define EXP_M2_4 1484190
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#define EXP_B_4 1051432828
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#define EXP_M1_5 394
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#define EXP_M2_5 1143049
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#define EXP_B_5 864288432
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struct SMU7_HystController_Data {
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uint16_t waterfall_up;
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uint16_t waterfall_down;
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uint16_t waterfall_limit;
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uint16_t release_cnt;
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uint16_t release_limit;
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uint16_t spare;
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};
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typedef struct SMU7_HystController_Data SMU7_HystController_Data;
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struct SMU75_PIDController {
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uint32_t Ki;
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int32_t LFWindupUpperLim;
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int32_t LFWindupLowerLim;
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uint32_t StatePrecision;
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uint32_t LfPrecision;
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uint32_t LfOffset;
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uint32_t MaxState;
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uint32_t MaxLfFraction;
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uint32_t StateShift;
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};
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typedef struct SMU75_PIDController SMU75_PIDController;
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struct SMU7_LocalDpmScoreboard {
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uint32_t PercentageBusy;
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int32_t PIDError;
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int32_t PIDIntegral;
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int32_t PIDOutput;
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uint32_t SigmaDeltaAccum;
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uint32_t SigmaDeltaOutput;
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uint32_t SigmaDeltaLevel;
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uint32_t UtilizationSetpoint;
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uint8_t TdpClampMode;
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uint8_t TdcClampMode;
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uint8_t ThermClampMode;
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uint8_t VoltageBusy;
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int8_t CurrLevel;
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int8_t TargLevel;
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uint8_t LevelChangeInProgress;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint32_t MinimumPerfSclk;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t GfxClkSlow;
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uint8_t GpioClampMode;
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uint8_t EnableModeSwitchRLCNotification;
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uint8_t EnabledLevelsChange;
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uint8_t DteClampMode;
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uint8_t FpsClampMode;
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uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_GRAPHICS];
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uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_GRAPHICS];
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void (*TargetStateCalculator)(uint8_t);
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void (*SavedTargetStateCalculator)(uint8_t);
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint8_t FpsEnabled;
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uint8_t MaxPerfLevel;
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uint8_t AllowLowClkInterruptToHost;
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uint8_t FpsRunning;
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uint32_t MaxAllowedFrequency;
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uint32_t FilteredSclkFrequency;
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uint32_t LastSclkFrequency;
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uint32_t FilteredSclkFrequencyCnt;
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uint8_t MinPerfLevel;
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#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
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uint8_t ScksClampMode;
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uint8_t padding[2];
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#else
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uint8_t padding[3];
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#endif
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uint16_t FpsAlpha;
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uint16_t DeltaTime;
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uint32_t CurrentFps;
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uint32_t FilteredFps;
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uint32_t FrameCount;
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uint32_t FrameCountLast;
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uint16_t FpsTargetScalar;
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uint16_t FpsWaterfallLimitScalar;
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uint16_t FpsAlphaScalar;
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uint16_t spare8;
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SMU7_HystController_Data HystControllerData;
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};
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typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
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#define SMU7_MAX_VOLTAGE_CLIENTS 12
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typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
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#define VDDC_MASK 0x00007FFF
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#define VDDC_SHIFT 0
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#define VDDCI_MASK 0x3FFF8000
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#define VDDCI_SHIFT 15
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#define PHASES_MASK 0xC0000000
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#define PHASES_SHIFT 30
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typedef uint32_t SMU_VoltageLevel;
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struct SMU7_VoltageScoreboard {
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SMU_VoltageLevel TargetVoltage;
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uint16_t MaxVid;
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uint8_t HighestVidOffset;
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uint8_t CurrentVidOffset;
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uint16_t CurrentVddc;
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uint16_t CurrentVddci;
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uint8_t ControllerBusy;
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uint8_t CurrentVid;
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uint8_t CurrentVddciVid;
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uint8_t padding;
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SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
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SMU_VoltageLevel TargetVoltageState;
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uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
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uint8_t padding2;
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uint8_t padding3;
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uint8_t ControllerEnable;
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uint8_t ControllerRunning;
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uint16_t CurrentStdVoltageHiSidd;
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uint16_t CurrentStdVoltageLoSidd;
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uint8_t OverrideVoltage;
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uint8_t padding4;
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uint8_t padding5;
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uint8_t CurrentPhases;
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VoltageChangeHandler_t ChangeVddc;
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VoltageChangeHandler_t ChangeVddci;
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VoltageChangeHandler_t ChangePhase;
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VoltageChangeHandler_t ChangeMvdd;
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VoltageChangeHandler_t functionLinks[6];
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uint16_t * VddcFollower1;
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int16_t Driver_OD_RequestedVidOffset1;
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int16_t Driver_OD_RequestedVidOffset2;
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};
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typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
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#define SMU7_MAX_PCIE_LINK_SPEEDS 3
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struct SMU7_PCIeLinkSpeedScoreboard {
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t CurrentLinkSpeed;
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uint8_t EnabledLevelsChange;
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint16_t AutoDpmCount;
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uint8_t DpmMode;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t CurrentLinkLevel;
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};
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typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
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#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
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#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
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#define SMU7_SCALE_I 7
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#define SMU7_SCALE_R 12
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struct SMU7_PowerScoreboard {
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uint32_t GpuPower;
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uint32_t VddcPower;
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uint32_t VddcVoltage;
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uint32_t VddcCurrent;
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uint32_t VddciPower;
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uint32_t VddciVoltage;
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uint32_t VddciCurrent;
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uint32_t RocPower;
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uint16_t Telemetry_1_slope;
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uint16_t Telemetry_2_slope;
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int32_t Telemetry_1_offset;
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int32_t Telemetry_2_offset;
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uint8_t MCLK_patch_flag;
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uint8_t reserved[3];
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};
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typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
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#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
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#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
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#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
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#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
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#define SMU7_UVD_DPM_CONFIG_MASK 0x10
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#define SMU7_VCE_DPM_CONFIG_MASK 0x20
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#define SMU7_ACP_DPM_CONFIG_MASK 0x40
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#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
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#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
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#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
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#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
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#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
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#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
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#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
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#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
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struct SMU75_SoftRegisters {
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uint32_t RefClockFrequency;
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uint32_t PmTimerPeriod;
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uint32_t FeatureEnables;
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#if defined (SMU__DGPU_ONLY)
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uint32_t PreVBlankGap;
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uint32_t VBlankTimeout;
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uint32_t TrainTimeGap;
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uint32_t MvddSwitchTime;
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uint32_t LongestAcpiTrainTime;
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uint32_t AcpiDelay;
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uint32_t G5TrainTime;
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uint32_t DelayMpllPwron;
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uint32_t VoltageChangeTimeout;
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#endif
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uint32_t HandshakeDisables;
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uint8_t DisplayPhy1Config;
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uint8_t DisplayPhy2Config;
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uint8_t DisplayPhy3Config;
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uint8_t DisplayPhy4Config;
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uint8_t DisplayPhy5Config;
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uint8_t DisplayPhy6Config;
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uint8_t DisplayPhy7Config;
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uint8_t DisplayPhy8Config;
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uint32_t AverageGraphicsActivity;
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uint32_t AverageMemoryActivity;
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uint32_t AverageGioActivity;
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uint8_t SClkDpmEnabledLevels;
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uint8_t MClkDpmEnabledLevels;
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uint8_t LClkDpmEnabledLevels;
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uint8_t PCIeDpmEnabledLevels;
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uint8_t UVDDpmEnabledLevels;
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uint8_t SAMUDpmEnabledLevels;
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uint8_t ACPDpmEnabledLevels;
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uint8_t VCEDpmEnabledLevels;
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uint32_t DRAM_LOG_ADDR_H;
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uint32_t DRAM_LOG_ADDR_L;
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uint32_t DRAM_LOG_PHY_ADDR_H;
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uint32_t DRAM_LOG_PHY_ADDR_L;
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uint32_t DRAM_LOG_BUFF_SIZE;
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uint32_t UlvEnterCount;
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uint32_t UlvTime;
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uint32_t UcodeLoadStatus;
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uint32_t AllowMvddSwitch;
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uint8_t Activity_Weight;
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uint8_t Reserved8[3];
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};
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typedef struct SMU75_SoftRegisters SMU75_SoftRegisters;
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struct SMU75_Firmware_Header {
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uint32_t Digest[5];
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uint32_t Version;
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uint32_t HeaderSize;
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uint32_t Flags;
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uint32_t EntryPoint;
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uint32_t CodeSize;
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uint32_t ImageSize;
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uint32_t Rtos;
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uint32_t SoftRegisters;
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uint32_t DpmTable;
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uint32_t FanTable;
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uint32_t CacConfigTable;
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uint32_t CacStatusTable;
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|
uint32_t mcRegisterTable;
|
|
uint32_t mcArbDramTimingTable;
|
|
uint32_t PmFuseTable;
|
|
uint32_t Globals;
|
|
uint32_t ClockStretcherTable;
|
|
uint32_t VftTable;
|
|
uint32_t Reserved1;
|
|
uint32_t AvfsCksOff_AvfsGbvTable;
|
|
uint32_t AvfsCksOff_BtcGbvTable;
|
|
uint32_t MM_AvfsTable;
|
|
uint32_t PowerSharingTable;
|
|
uint32_t AvfsTable;
|
|
uint32_t AvfsCksOffGbvTable;
|
|
uint32_t AvfsMeanNSigma;
|
|
uint32_t AvfsSclkOffsetTable;
|
|
uint32_t Reserved[12];
|
|
uint32_t Signature;
|
|
};
|
|
|
|
typedef struct SMU75_Firmware_Header SMU75_Firmware_Header;
|
|
|
|
#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
|
|
|
|
enum DisplayConfig {
|
|
PowerDown = 1,
|
|
DP54x4,
|
|
DP54x2,
|
|
DP54x1,
|
|
DP27x4,
|
|
DP27x2,
|
|
DP27x1,
|
|
HDMI297,
|
|
HDMI162,
|
|
LVDS,
|
|
DP324x4,
|
|
DP324x2,
|
|
DP324x1
|
|
};
|
|
|
|
#define MC_BLOCK_COUNT 1
|
|
#define CPL_BLOCK_COUNT 5
|
|
#define SE_BLOCK_COUNT 15
|
|
#define GC_BLOCK_COUNT 24
|
|
|
|
struct SMU7_Local_Cac {
|
|
uint8_t BlockId;
|
|
uint8_t SignalId;
|
|
uint8_t Threshold;
|
|
uint8_t Padding;
|
|
};
|
|
|
|
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
|
|
|
|
struct SMU7_Local_Cac_Table {
|
|
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
|
|
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
|
|
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
|
|
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
|
|
};
|
|
|
|
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
|
|
|
|
#pragma pack(pop)
|
|
|
|
#define CG_SYS_BITMASK_FIRST_BIT 0
|
|
#define CG_SYS_BITMASK_LAST_BIT 10
|
|
#define CG_SYS_BIF_MGLS_SHIFT 0
|
|
#define CG_SYS_ROM_SHIFT 1
|
|
#define CG_SYS_MC_MGCG_SHIFT 2
|
|
#define CG_SYS_MC_MGLS_SHIFT 3
|
|
#define CG_SYS_SDMA_MGCG_SHIFT 4
|
|
#define CG_SYS_SDMA_MGLS_SHIFT 5
|
|
#define CG_SYS_DRM_MGCG_SHIFT 6
|
|
#define CG_SYS_HDP_MGCG_SHIFT 7
|
|
#define CG_SYS_HDP_MGLS_SHIFT 8
|
|
#define CG_SYS_DRM_MGLS_SHIFT 9
|
|
#define CG_SYS_BIF_MGCG_SHIFT 10
|
|
|
|
#define CG_SYS_BIF_MGLS_MASK 0x1
|
|
#define CG_SYS_ROM_MASK 0x2
|
|
#define CG_SYS_MC_MGCG_MASK 0x4
|
|
#define CG_SYS_MC_MGLS_MASK 0x8
|
|
#define CG_SYS_SDMA_MGCG_MASK 0x10
|
|
#define CG_SYS_SDMA_MGLS_MASK 0x20
|
|
#define CG_SYS_DRM_MGCG_MASK 0x40
|
|
#define CG_SYS_HDP_MGCG_MASK 0x80
|
|
#define CG_SYS_HDP_MGLS_MASK 0x100
|
|
#define CG_SYS_DRM_MGLS_MASK 0x200
|
|
#define CG_SYS_BIF_MGCG_MASK 0x400
|
|
|
|
#define CG_GFX_BITMASK_FIRST_BIT 16
|
|
#define CG_GFX_BITMASK_LAST_BIT 24
|
|
|
|
#define CG_GFX_CGCG_SHIFT 16
|
|
#define CG_GFX_CGLS_SHIFT 17
|
|
#define CG_CPF_MGCG_SHIFT 18
|
|
#define CG_RLC_MGCG_SHIFT 19
|
|
#define CG_GFX_OTHERS_MGCG_SHIFT 20
|
|
#define CG_GFX_3DCG_SHIFT 21
|
|
#define CG_GFX_3DLS_SHIFT 22
|
|
#define CG_GFX_RLC_LS_SHIFT 23
|
|
#define CG_GFX_CP_LS_SHIFT 24
|
|
|
|
#define CG_GFX_CGCG_MASK 0x00010000
|
|
#define CG_GFX_CGLS_MASK 0x00020000
|
|
#define CG_CPF_MGCG_MASK 0x00040000
|
|
#define CG_RLC_MGCG_MASK 0x00080000
|
|
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
|
|
#define CG_GFX_3DCG_MASK 0x00200000
|
|
#define CG_GFX_3DLS_MASK 0x00400000
|
|
#define CG_GFX_RLC_LS_MASK 0x00800000
|
|
#define CG_GFX_CP_LS_MASK 0x01000000
|
|
|
|
|
|
#define VRCONF_VDDC_MASK 0x000000FF
|
|
#define VRCONF_VDDC_SHIFT 0
|
|
#define VRCONF_VDDGFX_MASK 0x0000FF00
|
|
#define VRCONF_VDDGFX_SHIFT 8
|
|
#define VRCONF_VDDCI_MASK 0x00FF0000
|
|
#define VRCONF_VDDCI_SHIFT 16
|
|
#define VRCONF_MVDD_MASK 0xFF000000
|
|
#define VRCONF_MVDD_SHIFT 24
|
|
|
|
#define VR_MERGED_WITH_VDDC 0
|
|
#define VR_SVI2_PLANE_1 1
|
|
#define VR_SVI2_PLANE_2 2
|
|
#define VR_SMIO_PATTERN_1 3
|
|
#define VR_SMIO_PATTERN_2 4
|
|
#define VR_STATIC_VOLTAGE 5
|
|
|
|
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
|
|
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
|
|
|
|
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
|
|
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
|
|
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
|
|
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
|
|
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
|
|
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
|
|
|
|
struct SMU_ClockStretcherDataTableEntry {
|
|
uint8_t minVID;
|
|
uint8_t maxVID;
|
|
|
|
uint16_t setting;
|
|
};
|
|
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
|
|
|
|
struct SMU_ClockStretcherDataTable {
|
|
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
|
|
};
|
|
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
|
|
|
|
struct SMU_CKS_LOOKUPTableEntry {
|
|
uint16_t minFreq;
|
|
uint16_t maxFreq;
|
|
|
|
uint8_t setting;
|
|
uint8_t padding[3];
|
|
};
|
|
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
|
|
|
|
struct SMU_CKS_LOOKUPTable {
|
|
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
|
|
};
|
|
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
|
|
|
|
struct AgmAvfsData_t {
|
|
uint16_t avgPsmCount[28];
|
|
uint16_t minPsmCount[28];
|
|
};
|
|
typedef struct AgmAvfsData_t AgmAvfsData_t;
|
|
|
|
enum VFT_COLUMNS {
|
|
SCLK0,
|
|
SCLK1,
|
|
SCLK2,
|
|
SCLK3,
|
|
SCLK4,
|
|
SCLK5,
|
|
SCLK6,
|
|
SCLK7,
|
|
|
|
NUM_VFT_COLUMNS
|
|
};
|
|
enum {
|
|
SCS_FUSE_T0,
|
|
SCS_FUSE_T1,
|
|
NUM_SCS_FUSE_TEMPERATURE
|
|
};
|
|
enum {
|
|
SCKS_ON,
|
|
SCKS_OFF,
|
|
NUM_SCKS_STATE_TYPES
|
|
};
|
|
|
|
#define VFT_TABLE_DEFINED
|
|
|
|
#define TEMP_RANGE_MAXSTEPS 12
|
|
struct VFT_CELL_t {
|
|
uint16_t Voltage;
|
|
};
|
|
|
|
typedef struct VFT_CELL_t VFT_CELL_t;
|
|
#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
|
|
struct SCS_CELL_t {
|
|
uint16_t PsmCnt[NUM_SCKS_STATE_TYPES];
|
|
};
|
|
typedef struct SCS_CELL_t SCS_CELL_t;
|
|
#endif
|
|
|
|
struct VFT_TABLE_t {
|
|
VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
|
|
uint16_t AvfsGbv [NUM_VFT_COLUMNS];
|
|
uint16_t BtcGbv [NUM_VFT_COLUMNS];
|
|
int16_t Temperature [TEMP_RANGE_MAXSTEPS];
|
|
|
|
#ifdef SMU__FIRMWARE_SCKS_PRESENT__1
|
|
SCS_CELL_t ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
|
|
#endif
|
|
|
|
uint8_t NumTemperatureSteps;
|
|
uint8_t padding[3];
|
|
};
|
|
typedef struct VFT_TABLE_t VFT_TABLE_t;
|
|
|
|
#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
|
|
#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
|
|
|
|
struct GB_VDROOP_TABLE_t {
|
|
int32_t a0;
|
|
int32_t a1;
|
|
int32_t a2;
|
|
uint32_t spare;
|
|
};
|
|
typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
|
|
|
|
struct SMU_QuadraticCoeffs {
|
|
int32_t m1;
|
|
int32_t b;
|
|
|
|
int16_t m2;
|
|
uint8_t m1_shift;
|
|
uint8_t m2_shift;
|
|
};
|
|
typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
|
|
|
|
struct AVFS_Margin_t {
|
|
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
|
|
};
|
|
typedef struct AVFS_Margin_t AVFS_Margin_t;
|
|
|
|
struct AVFS_CksOff_Gbv_t {
|
|
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
|
|
};
|
|
typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
|
|
|
|
struct AVFS_CksOff_AvfsGbv_t {
|
|
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
|
|
};
|
|
typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t;
|
|
|
|
struct AVFS_CksOff_BtcGbv_t {
|
|
VFT_CELL_t Cell[NUM_VFT_COLUMNS];
|
|
};
|
|
typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t;
|
|
|
|
struct AVFS_meanNsigma_t {
|
|
uint32_t Aconstant[3];
|
|
uint16_t DC_tol_sigma;
|
|
uint16_t Platform_mean;
|
|
uint16_t Platform_sigma;
|
|
uint16_t PSM_Age_CompFactor;
|
|
uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
|
|
};
|
|
typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
|
|
|
|
struct AVFS_Sclk_Offset_t {
|
|
uint16_t Sclk_Offset[8];
|
|
};
|
|
typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
|
|
|
|
struct Power_Sharing_t {
|
|
uint32_t EnergyCounter;
|
|
uint32_t EngeryThreshold;
|
|
uint64_t AM_SCLK_CNT;
|
|
uint64_t AM_0_BUSY_CNT;
|
|
};
|
|
typedef struct Power_Sharing_t Power_Sharing_t;
|
|
|
|
|
|
#endif
|
|
|
|
|