Chris Park 83bb503275 drm/amd/display: Correct Slice reset calculation ... [Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-03-31 23:05:53 -04:00
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dc_dsc.c	drm/amd/display: Correct Slice reset calculation	2022-03-31 23:05:53 -04:00
dscc_types.h	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
Makefile	drm/amd/display: move FPU associated DSC code to DML folder	2021-10-28 14:26:14 -04:00
rc_calc.c	drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC	2021-11-24 14:06:52 -05:00
rc_calc.h	drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC	2021-11-24 14:06:52 -05:00
rc_calc_dpi.c	drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC	2021-11-24 14:06:52 -05:00