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linux/drivers/gpu/drm/amd/include/asic_reg/dcn
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Qingqing Zhuo 5b723b1230 drm/amd/include: add DCN 3.1.5 registers 
Add DCN 3.1.5 and DPCS 4.2.2 register headers.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Change-Id: I5588a1c422ae384cc76aa42380545dfc1aad1948
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-18 14:07:00 -05:00
..
dcn_1_0_offset.h drm/amd/include: Add HUBPREQ_DEBUG register offsets 2019-04-23 17:27:08 -05:00
dcn_1_0_sh_mask.h drm/amdgpu: Add CM_TEST_DEBUG regs for DCN 2018-04-11 13:07:35 -05:00
dcn_2_0_0_offset.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_0_0_sh_mask.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_0_3_offset.h drm/amdgpu: add cyan_skillfish asic header files 2021-09-29 17:30:00 -04:00
dcn_2_0_3_sh_mask.h drm/amdgpu: add cyan_skillfish asic header files 2021-09-29 17:30:00 -04:00
dcn_2_1_0_offset.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_1_0_sh_mask.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_3_0_0_offset.h drm/amd/amdgpu: Add missing BASE_IDX to dcn register 2021-03-05 15:11:32 -05:00
dcn_3_0_0_sh_mask.h drm/amd/display: remove unintended executable mode 2020-08-24 12:23:02 -04:00
dcn_3_0_1_offset.h drm/amdgpu: add vangogh asic header files (v2) 2020-10-05 15:14:02 -04:00
dcn_3_0_1_sh_mask.h drm/amd/display: Add interface to get Calibrated Avg Level from FIFO 2021-06-15 17:25:41 -04:00
dcn_3_0_2_offset.h drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10 14:15:08 -05:00
dcn_3_0_2_sh_mask.h drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10 14:15:08 -05:00
dcn_3_0_3_offset.h drm/amd/display: Edit license info for beige goby DC files 2021-05-19 22:42:04 -04:00
dcn_3_0_3_sh_mask.h drm/amd/display: Edit license info for beige goby DC files 2021-05-19 22:42:04 -04:00
dcn_3_1_2_offset.h drm/amd/display: Disable hdmistream and hdmichar clocks 2021-10-19 17:20:28 -04:00
dcn_3_1_2_sh_mask.h drm/amd/display: Disable hdmistream and hdmichar clocks 2021-10-19 17:20:28 -04:00
dcn_3_1_5_offset.h drm/amd/include: add DCN 3.1.5 registers 2022-02-18 14:07:00 -05:00
dcn_3_1_5_sh_mask.h drm/amd/include: add DCN 3.1.5 registers 2022-02-18 14:07:00 -05:00
dcn_3_1_6_offset.h drm/amd/include: Add register headers for DCN 3.1.6 2022-02-17 15:44:45 -05:00
dcn_3_1_6_sh_mask.h drm/amd/include: Add register headers for DCN 3.1.6 2022-02-17 15:44:45 -05:00