78d9b458cc
Add CRC support to DPU, which is currently not supported by this driver. Only supports CRC for CRTC for now, but will extend support to other blocks later on. Changes in v2: - Added kfree() calls for return paths in dpu_crtc_get_crc() - Propogated error code for dpu_crtc_get_crc() - Renamed skip_count - Removed dpu_crtc_is_valid_crc_source() - Removed wait for commit in dpu_crtc_set_crc_source() - Moved crc_source from struct dpu_crtc to struct dpu_crtc_state - Moved CRC register constants from dpu_hw_util.h to dpu_hw_lm.c Validated with IGT kms_pipe_crc_basic, and kms_cursor_crc Test: kms_pipe_crc_basic Subtests Passed: - bad-source - read-crc-pipe-A - read-crc-pipe-A-frame-sequence - nonblocking-crc-pipe-A - nonblocking-crc-pipe-A-frame-sequence - disable-crc-after-crtc-pipe-A[1] - compare-crc-sanitycheck-pipe-A[1] Rest skipped Test: kms_cursor_crc Subtests Passed: - pipe-A-cursor-size-change - pipe-A-cursor-alpha-opaque - pipe-A-cursor-alpha-transparent Subtests Failed: - pipe-A-cursor-dpms - pipe-A-cursor-*-onscreen - pipe-A-cursor-*-offscreen Rest skipped Tested on Qualcomm RB3 (debian, sdm845), Qualcomm RB5 (debian, qrb5165) Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jessica Zhang <jesszhan@codeaurora.org> [1] Skipped on RB5 due to issue related to DPMS. Planning to upload a fix for this in the future. Link: https://lore.kernel.org/r/20211019224822.25940-1-jesszhan@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
113 lines
2.6 KiB
C
113 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_LM_H
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#define _DPU_HW_LM_H
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_blk.h"
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struct dpu_hw_mixer;
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struct dpu_hw_mixer_cfg {
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u32 out_width;
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u32 out_height;
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bool right_mixer;
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int flags;
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};
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struct dpu_hw_color3_cfg {
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u8 keep_fg[DPU_STAGE_MAX];
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};
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/**
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*
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* struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_lm_ops {
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/*
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* Sets up mixer output width and height
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* and border color if enabled
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*/
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void (*setup_mixer_out)(struct dpu_hw_mixer *ctx,
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struct dpu_hw_mixer_cfg *cfg);
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/*
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* Alpha blending configuration
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* for the specified stage
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*/
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void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
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uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
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/*
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* Alpha color component selection from either fg or bg
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*/
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void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op);
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/**
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* setup_border_color : enable/disable border color
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*/
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void (*setup_border_color)(struct dpu_hw_mixer *ctx,
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struct dpu_mdss_color *color,
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u8 border_en);
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/**
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* setup_misr: Enable/disable MISR
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*/
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void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);
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/**
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* collect_misr: Read MISR signature
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*/
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int (*collect_misr)(struct dpu_hw_mixer *ctx, u32 *misr_value);
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};
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struct dpu_hw_mixer {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* lm */
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enum dpu_lm idx;
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const struct dpu_lm_cfg *cap;
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const struct dpu_mdp_cfg *mdp;
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const struct dpu_ctl_cfg *ctl;
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/* ops */
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struct dpu_hw_lm_ops ops;
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/* store mixer info specific to display */
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struct dpu_hw_mixer_cfg cfg;
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};
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/**
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* to_dpu_hw_mixer - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_mixer, base);
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}
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/**
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* dpu_hw_lm_init(): Initializes the mixer hw driver object.
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* should be called once before accessing every mixer.
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* @idx: mixer index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_lm_destroy(): Destroys layer mixer driver context
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* @lm: Pointer to LM driver context
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*/
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void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm);
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#endif /*_DPU_HW_LM_H */
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