5752c921d2
DPU driver contains code to parse clock items from device tree into special data struct and then enable/disable/set rate for the clocks using that data struct. However the DPU driver itself uses only parsing and enabling/disabling part (the rate setting is used by DP driver). Move this implementation to the DP driver (which actually uses rate setting) and replace hand-coded enable/disable/get loops in the DPU with the respective clk_bulk operations. Put operation is removed completely because, it is handled using devres instead. DP implementation is unchanged for now. Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # RB3 (sdm845) and RB5 (qrb5165) Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220217055529.499829-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DP_CLK_UTIL_H__
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#define __DP_CLK_UTIL_H__
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#define DEV_DBG(fmt, args...) pr_debug(fmt, ##args)
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#define DEV_INFO(fmt, args...) pr_info(fmt, ##args)
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#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args)
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#define DEV_ERR(fmt, args...) pr_err(fmt, ##args)
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enum dss_clk_type {
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DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
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DSS_CLK_PCLK,
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};
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struct dss_clk {
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struct clk *clk; /* clk handle */
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char clk_name[32];
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enum dss_clk_type type;
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unsigned long rate;
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unsigned long max_rate;
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};
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struct dss_module_power {
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unsigned int num_clk;
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struct dss_clk *clk_config;
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};
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int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
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void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
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int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
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int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
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#endif /* __DP_CLK_UTIL_H__ */
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