1da8779c00
Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is composed by: -STM32MP131: -core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX -storage: 3*SDMCC, 1*QSPI, FMC -com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART -audio: 2*SAI -network: 1*ETH(GMAC) -STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 -STM32MP135: STM32MP133 + DCMIPP, LTDC A second diversity layer exists for security features: -STM32MP13xY, "Y" gives information: -Y = A/D means no cryp IP and no secure boot. -Y = C/F means cryp IP + secure boot. This commit adds basic peripheral. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
37 lines
1.1 KiB
Text
37 lines
1.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp131.dtsi"
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/ {
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soc {
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&clk_hse>, <&clk_pll4_r>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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m_can2: can@4400f000 {
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compatible = "bosch,m_can";
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reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&clk_hse>, <&clk_pll4_r>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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};
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};
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