9d7b307862
"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not
set until bitstream programming time.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
88 lines
1.3 KiB
Text
88 lines
1.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/dts-v1/;
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#include "microchip-mpfs.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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/ {
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model = "Microchip PolarFire-SoC Icicle Kit";
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compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
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aliases {
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ethernet0 = &emac1;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <RTCCLK_FREQ>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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clocks = <&clkcfg 26>;
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};
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};
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&refclk {
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clock-frequency = <600000000>;
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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&mmc {
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status = "okay";
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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};
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&emac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy0: ethernet-phy@8 {
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reg = <8>;
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ti,fifo-depth = <0x01>;
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};
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};
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&emac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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ti,fifo-depth = <0x01>;
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};
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};
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