f5c7e77970
Adjust removal control flow for smu v13_0_2:
During amdgpu uninstallation, when removing the first
device, the kernel needs to first send a mode1reset message
to all gpu devices. Otherwise, smu initialization will fail
the next time amdgpu is installed.
V2:
1. Update commit comments.
2. Remove the global variable amdgpu_device_remove_cnt
and add a variable to the structure amdgpu_hive_info.
3. Use hive to detect the first removed device instead of
a global variable.
V3:
1. Update commit comments.
2. Split a patch into multiple patches.
3. The current patch does:
a. Add a work mode of AMDGPU_RESET_FOR_DEVICE_REMOVE into
the existing gpu recover path, which make all devices
in hive list only have HW reset but no resume (except
the base IP).
b. Call AMDGPU_RESET_FOR_DEVICE_REMOVE and
AMDGPU_NEED_FULL_RESET mode of amdgpu_device_gpu_recover
in amdgpu_pci_remove when removing the first device in
hive list.
c. When removing the first device, the IP blocks keyword
function call sequence is as follows:
.suspend->mode1reset->.resume(basic ip)->.hw_fini->.early_fini->.sw_fini.
^ |
|-<----------<---------<----|
The first three sequences are because of a call to
amdgpu_device_gpu_recover. The three sequences will be
executed in a loop until all devices in the hive list
are iterated.
The sequences starting from .hw_fini only apply to the
first device. Since .suspend has been called before,
except the resumed phase1 basic ip blocks, all other ip
blocks .hw_fini of current device will do nothing.
d. When removing other devices, the calling sequences is the
same as legacy:
.hw_fini -> .early_fini -> .sw_fini.
Since .suspend has been called when removing the first device,
except the resumed phase1 basic ip blocks, all of other ip
blocks .hw_fini of current device will do nothing.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_XGMI_H__
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#define __AMDGPU_XGMI_H__
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#include <drm/task_barrier.h>
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#include "amdgpu_psp.h"
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#include "amdgpu_ras.h"
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struct amdgpu_hive_info {
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struct kobject kobj;
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uint64_t hive_id;
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struct list_head device_list;
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struct list_head node;
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atomic_t number_devices;
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struct mutex hive_lock;
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int hi_req_count;
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struct amdgpu_device *hi_req_gpu;
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struct task_barrier tb;
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enum {
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AMDGPU_XGMI_PSTATE_MIN,
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AMDGPU_XGMI_PSTATE_MAX_VEGA20,
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AMDGPU_XGMI_PSTATE_UNKNOWN
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} pstate;
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struct amdgpu_reset_domain *reset_domain;
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uint32_t device_remove_count;
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};
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struct amdgpu_pcs_ras_field {
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const char *err_name;
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uint32_t pcs_err_mask;
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uint32_t pcs_err_shift;
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};
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extern struct amdgpu_xgmi_ras xgmi_ras;
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struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
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void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
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int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
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int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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uint64_t addr);
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static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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struct amdgpu_device *bo_adev)
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{
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return (amdgpu_use_xgmi_p2p &&
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adev != bo_adev &&
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adev->gmc.xgmi.hive_id &&
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adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
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}
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#endif
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