91e43ca009
The recent support for DPLL introduced by commit8a3a565ff2("ice: add admin commands to access cgu configuration") and commitd7999f5ea6("ice: implement dpll interface to control cgu") broke linking the ice driver if CONFIG_PTP_1588_CLOCK=n: ld: vmlinux.o: in function `ice_init_feature_support': (.text+0x8702b8): undefined reference to `ice_is_phy_rclk_present' ld: (.text+0x8702cd): undefined reference to `ice_is_cgu_present' ld: (.text+0x8702d9): undefined reference to `ice_is_clock_mux_present_e810t' ld: vmlinux.o: in function `ice_dpll_init_info_direct_pins': ice_dpll.c:(.text+0x894167): undefined reference to `ice_cgu_get_pin_freq_supp' ld: ice_dpll.c:(.text+0x894197): undefined reference to `ice_cgu_get_pin_name' ld: ice_dpll.c:(.text+0x8941a8): undefined reference to `ice_cgu_get_pin_type' ld: vmlinux.o: in function `ice_dpll_update_state': ice_dpll.c:(.text+0x894494): undefined reference to `ice_get_cgu_state' ld: vmlinux.o: in function `ice_dpll_init': (.text+0x8953d5): undefined reference to `ice_get_cgu_rclk_pin_info' The first commit broke things by calling functions in ice_init_feature_support that are compiled as part of ice_ptp_hw.o, including: * ice_is_phy_rclk_present * ice_is_clock_mux_present_e810t * ice_is_cgU_present The second commit continued the break by calling several CGU functions defined in ice_ptp_hw.c in the DPLL code. Because the ice_dpll.c file is compiled unconditionally, it will not link when CONFIG_PTP_1588_CLOCK=n. It might be possible to break this dependency and expose those functions without CONFIG_PTP_1588_CLOCK, but that is not clear to me. For the DPLL case, simply compile ice_dpll.o only when we have CONFIG_PTP_1588_CLOCK. Add stub no-op implementation of ice_dpll_init() and ice_dpll_uninit() when CONFIG_PTP_1588_CLOCK=n into ice_dpll.h The other functions are part of checking the netlist to see if hardware features are enabled. These checks don't really belong in ice_ptp_hw.c, and make more sense as part of the ice_common.c file. We already have ice_is_gps_in_netlist() in ice_common.c which is doing a similar check. Move the functions into ice_common.c and rename them to have the similar postfix of "in_netlist()" to be more expressive of what they are actually checking. This also makes the ice_find_netlist_node only called from within ice_common.c, so its safe to mark it static and stop declaring it in the ice_common.h header as well. Fixes:8a3a565ff2("ice: add admin commands to access cgu configuration") Fixes:d7999f5ea6("ice: implement dpll interface to control cgu") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309191214.TaYEct4H-lkp@intel.com Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Tested-by: Simon Horman <horms@kernel.org> # build-tested Link: https://lore.kernel.org/r/20231002185132.1575271-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
108 lines
3 KiB
C
108 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2022, Intel Corporation. */
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#ifndef _ICE_DPLL_H_
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#define _ICE_DPLL_H_
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#include "ice.h"
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#define ICE_DPLL_PRIO_MAX 0xF
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#define ICE_DPLL_RCLK_NUM_MAX 4
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/** ice_dpll_pin - store info about pins
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* @pin: dpll pin structure
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* @pf: pointer to pf, which has registered the dpll_pin
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* @idx: ice pin private idx
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* @num_parents: hols number of parent pins
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* @parent_idx: hold indexes of parent pins
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* @flags: pin flags returned from HW
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* @state: state of a pin
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* @prop: pin properties
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* @freq: current frequency of a pin
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*/
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struct ice_dpll_pin {
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struct dpll_pin *pin;
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struct ice_pf *pf;
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u8 idx;
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u8 num_parents;
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u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];
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u8 flags[ICE_DPLL_RCLK_NUM_MAX];
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u8 state[ICE_DPLL_RCLK_NUM_MAX];
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struct dpll_pin_properties prop;
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u32 freq;
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};
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/** ice_dpll - store info required for DPLL control
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* @dpll: pointer to dpll dev
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* @pf: pointer to pf, which has registered the dpll_device
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* @dpll_idx: index of dpll on the NIC
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* @input_idx: currently selected input index
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* @prev_input_idx: previously selected input index
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* @ref_state: state of dpll reference signals
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* @eec_mode: eec_mode dpll is configured for
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* @phase_shift: phase shift delay of a dpll
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* @input_prio: priorities of each input
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* @dpll_state: current dpll sync state
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* @prev_dpll_state: last dpll sync state
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* @active_input: pointer to active input pin
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* @prev_input: pointer to previous active input pin
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*/
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struct ice_dpll {
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struct dpll_device *dpll;
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struct ice_pf *pf;
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u8 dpll_idx;
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u8 input_idx;
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u8 prev_input_idx;
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u8 ref_state;
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u8 eec_mode;
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s64 phase_shift;
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u8 *input_prio;
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enum dpll_lock_status dpll_state;
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enum dpll_lock_status prev_dpll_state;
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enum dpll_mode mode;
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struct dpll_pin *active_input;
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struct dpll_pin *prev_input;
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};
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/** ice_dplls - store info required for CCU (clock controlling unit)
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* @kworker: periodic worker
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* @work: periodic work
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* @lock: locks access to configuration of a dpll
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* @eec: pointer to EEC dpll dev
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* @pps: pointer to PPS dpll dev
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* @inputs: input pins pointer
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* @outputs: output pins pointer
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* @rclk: recovered pins pointer
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* @num_inputs: number of input pins available on dpll
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* @num_outputs: number of output pins available on dpll
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* @cgu_state_acq_err_num: number of errors returned during periodic work
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* @base_rclk_idx: idx of first pin used for clock revocery pins
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* @clock_id: clock_id of dplls
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*/
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struct ice_dplls {
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struct kthread_worker *kworker;
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struct kthread_delayed_work work;
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struct mutex lock;
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struct ice_dpll eec;
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struct ice_dpll pps;
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struct ice_dpll_pin *inputs;
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struct ice_dpll_pin *outputs;
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struct ice_dpll_pin rclk;
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u8 num_inputs;
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u8 num_outputs;
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int cgu_state_acq_err_num;
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u8 base_rclk_idx;
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u64 clock_id;
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s32 input_phase_adj_max;
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s32 output_phase_adj_max;
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};
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
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void ice_dpll_init(struct ice_pf *pf);
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void ice_dpll_deinit(struct ice_pf *pf);
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#else
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static inline void ice_dpll_init(struct ice_pf *pf) { }
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static inline void ice_dpll_deinit(struct ice_pf *pf) { }
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#endif
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#endif
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