d14bc28af3
Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com> [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 lines
339 B
C
14 lines
339 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef _PCIE_QCOM_COMMON_H
|
|
#define _PCIE_QCOM_COMMON_H
|
|
|
|
struct dw_pcie;
|
|
|
|
void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci);
|
|
void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci);
|
|
|
|
#endif
|