e86e793c28
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).
As a step towards that, this patch migrates m68k to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.
While atomic_dec_and_test_lt() is not part of the common atomic API, it
is also given an `arch_` prefix for consistency.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210525140232.53872-21-mark.rutland@arm.com
136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ARCH_M68K_CMPXCHG__
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#define __ARCH_M68K_CMPXCHG__
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#include <linux/irqflags.h>
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((volatile struct __xchg_dummy *)(x))
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extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
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#ifndef CONFIG_RMW_INSNS
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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unsigned long flags, tmp;
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local_irq_save(flags);
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switch (size) {
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case 1:
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tmp = *(u8 *)ptr;
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*(u8 *)ptr = x;
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x = tmp;
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break;
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case 2:
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tmp = *(u16 *)ptr;
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*(u16 *)ptr = x;
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x = tmp;
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break;
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case 4:
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tmp = *(u32 *)ptr;
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*(u32 *)ptr = x;
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x = tmp;
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break;
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default:
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tmp = __invalid_xchg_size(x, ptr, size);
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break;
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}
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local_irq_restore(flags);
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return x;
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}
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#else
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"1:\n\t"
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"casb %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"1:\n\t"
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"casw %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"1:\n\t"
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"casl %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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default:
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x = __invalid_xchg_size(x, ptr, size);
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break;
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}
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return x;
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}
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#endif
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#define arch_xchg(ptr,x) ({(__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)));})
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#include <asm-generic/cmpxchg-local.h>
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#define arch_cmpxchg64_local(ptr, o, n) __generic_cmpxchg64_local((ptr), (o), (n))
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extern unsigned long __invalid_cmpxchg_size(volatile void *,
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unsigned long, unsigned long, int);
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#ifdef CONFIG_RMW_INSNS
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static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__ ("casb %0,%2,%1"
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: "=d" (old), "=m" (*(char *)p)
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: "d" (new), "0" (old), "m" (*(char *)p));
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break;
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case 2:
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__asm__ __volatile__ ("casw %0,%2,%1"
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: "=d" (old), "=m" (*(short *)p)
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: "d" (new), "0" (old), "m" (*(short *)p));
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break;
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case 4:
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__asm__ __volatile__ ("casl %0,%2,%1"
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: "=d" (old), "=m" (*(int *)p)
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: "d" (new), "0" (old), "m" (*(int *)p));
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break;
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default:
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old = __invalid_cmpxchg_size(p, old, new, size);
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break;
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}
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return old;
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}
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#define arch_cmpxchg(ptr, o, n) \
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({(__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr)));})
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#define arch_cmpxchg_local(ptr, o, n) \
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({(__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr)));})
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#define arch_cmpxchg64(ptr, o, n) arch_cmpxchg64_local((ptr), (o), (n))
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#else
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#include <asm-generic/cmpxchg.h>
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#endif
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#endif /* __ARCH_M68K_CMPXCHG__ */
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