a6a7cba17c
In general the delay should be added by the PHY instead of the MAC,
and this improves network stability on some boards which seem to
need different delay.
Fixes: 387b3bbac5 ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
Cc: stable@vger.kernel.org # 6.6+
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20250119091154.1110762-1-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
41 lines
939 B
Text
41 lines
939 B
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2016 Xunlong Software. Co., Ltd.
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* (http://www.orangepi.org)
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*
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* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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*/
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/dts-v1/;
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#include "rk3328-orangepi-r1-plus.dtsi"
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/ {
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model = "Xunlong Orange Pi R1 Plus LTS";
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compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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};
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&gmac2io {
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phy-handle = <&yt8531c>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio {
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yt8531c: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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motorcomm,auto-sleep-disabled;
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motorcomm,clk-out-frequency-hz = <125000000>;
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motorcomm,keep-pll-enabled;
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motorcomm,rx-clk-drv-microamp = <5020>;
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motorcomm,rx-data-drv-microamp = <5020>;
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pinctrl-0 = <ð_phy_reset_pin>;
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pinctrl-names = "default";
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reset-assert-us = <15000>;
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reset-deassert-us = <50000>;
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reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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};
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};
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};
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