7d1163fc08
Commitda92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") enabled the mmu600_pcie IOMMU, both in the normal case (when all PCIe controllers are running in Root Complex mode) and in the case when running the pcie3x4 PCIe controller in Endpoint mode. There have been no issues detected when running the PCIe controllers in Root Complex mode. During PCI probe time, we will add a SID to the IOMMU for each PCI device enumerated on the bus, including the root port itself. However, when running the pcie3x4 PCIe controller in Endpoint mode, we will only add a single SID to the IOMMU (the SID specified in the iommus DT property). The enablement of IOMMU in endpoint mode was verified on setup with two Rock 5b:s, where the BDF of the Root Complex has BDF (00:00.0). A Root Complex sending a TLP to the Endpoint will have Requester ID set to the BDF of the initiator. On the EP side, the Requester ID will then be used as the SID. This works fine if the Root Complex has a BDF that matches the iommus DT property, however, if the Root Complex has any other BDF, we will see something like: arm-smmu-v3 fc900000.iommu: event: C_BAD_STREAMID client: (unassigned sid) sid: 0x1600 ssid: 0x0 on the endpoint side. For PCIe controllers running in endpoint mode that always uses the incoming Requester ID as the SID, the iommus DT property simply isn't a viable solution. (Neither is iommu-map a viable solution, as there is no enumeration done on the endpoint side.) Thus, partly revert commitda92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") by disabling the PCI IOMMU when running the pcie3x4 PCIe controller in Endpoint mode. Since the PCI IOMMU is working as expected in the normal case, keep it enabled when running all PCIe controllers in Root Complex mode. Fixes:da92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") Signed-off-by: Niklas Cassel <cassel@kernel.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20250207143900.2047949-2-cassel@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
451 lines
14 KiB
Text
451 lines
14 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3588-base.dtsi"
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#include "rk3588-extra-pinctrl.dtsi"
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/ {
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usb_host1_xhci: usb@fc400000 {
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compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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<&cru ACLK_USB3OTG1>;
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clock-names = "ref_clk", "suspend_clk", "bus_clk";
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dr_mode = "otg";
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phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG1>;
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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};
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pcie30_phy_grf: syscon@fd5b8000 {
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compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfd5b8000 0x0 0x10000>;
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};
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pipe_phy1_grf: syscon@fd5c0000 {
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compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5c0000 0x0 0x100>;
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};
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usbdpphy1_grf: syscon@fd5cc000 {
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compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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reg = <0x0 0xfd5cc000 0x0 0x4000>;
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};
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usb2phy1_grf: syscon@fd5d4000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfd5d4000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy1: usb2phy@4000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x4000 0x10>;
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#clock-cells = <0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
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resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
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reset-names = "phy", "apb";
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status = "disabled";
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u2phy1_otg: otg-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 22>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO0>;
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resets = <&cru SRST_M_I2S8_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s6_8ch: i2s@fddf4000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf4000 0x0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 4>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S6_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s7_8ch: i2s@fddf8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf8000 0x0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 21>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S7_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s10_8ch: i2s@fde00000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfde00000 0x0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 24>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S10_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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pcie3x4: pcie@fe150000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0x0f>;
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
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<0 0 0 2 &pcie3x4_intc 1>,
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<0 0 0 3 &pcie3x4_intc 2>,
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<0 0 0 4 &pcie3x4_intc 3>;
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linux,pci-domain = <0>;
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max-link-speed = <3>;
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msi-map = <0x0000 &its1 0x0000 0x1000>;
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iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
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reg = <0xa 0x40000000 0x0 0x00400000>,
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<0x0 0xfe150000 0x0 0x00010000>,
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<0x0 0xf0000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie3x4_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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pcie3x4_ep: pcie-ep@fe150000 {
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compatible = "rockchip,rk3588-pcie-ep";
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reg = <0xa 0x40000000 0x0 0x00100000>,
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<0xa 0x40100000 0x0 0x00100000>,
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<0x0 0xfe150000 0x0 0x00010000>,
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<0x9 0x00000000 0x0 0x40000000>,
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<0xa 0x40300000 0x0 0x00100000>;
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reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err",
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"dma0", "dma1", "dma2", "dma3";
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max-link-speed = <3>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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};
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pcie3x2: pcie@fe160000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
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<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
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<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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<0 0 0 2 &pcie3x2_intc 1>,
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<0 0 0 3 &pcie3x2_intc 2>,
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<0 0 0 4 &pcie3x2_intc 3>;
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linux,pci-domain = <1>;
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max-link-speed = <3>;
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msi-map = <0x1000 &its1 0x1000 0x1000>;
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iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
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reg = <0xa 0x40400000 0x0 0x00400000>,
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<0x0 0xfe160000 0x0 0x00010000>,
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<0x0 0xf1000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie3x2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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pcie2x1l0: pcie@fe170000 {
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compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
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<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
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<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
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<0 0 0 2 &pcie2x1l0_intc 1>,
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<0 0 0 3 &pcie2x1l0_intc 2>,
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<0 0 0 4 &pcie2x1l0_intc 3>;
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its0 0x2000 0x1000>;
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iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy1_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
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<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
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<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
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reg = <0xa 0x40800000 0x0 0x00400000>,
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<0x0 0xfe170000 0x0 0x00010000>,
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<0x0 0xf2000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
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reset-names = "pwr", "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie2x1l0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
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};
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "macirq", "eth_wake_irq";
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clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
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<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
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<&cru CLK_GMAC0_PTP_REF>;
|
|
clock-names = "stmmaceth", "clk_mac_ref",
|
|
"pclk_mac", "aclk_mac",
|
|
"ptp_ref";
|
|
power-domains = <&power RK3588_PD_GMAC>;
|
|
resets = <&cru SRST_A_GMAC0>;
|
|
reset-names = "stmmaceth";
|
|
rockchip,grf = <&sys_grf>;
|
|
rockchip,php-grf = <&php_grf>;
|
|
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
snps,mixed-burst;
|
|
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
snps,tso;
|
|
status = "disabled";
|
|
|
|
mdio0: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
};
|
|
|
|
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
snps,wr_osr_lmt = <4>;
|
|
snps,rd_osr_lmt = <8>;
|
|
};
|
|
|
|
gmac0_mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <2>;
|
|
queue0 {};
|
|
queue1 {};
|
|
};
|
|
|
|
gmac0_mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <2>;
|
|
queue0 {};
|
|
queue1 {};
|
|
};
|
|
};
|
|
|
|
sata1: sata@fe220000 {
|
|
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
reg = <0 0xfe220000 0 0x1000>;
|
|
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
|
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
|
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
ports-implemented = <0x1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sata-port@0 {
|
|
reg = <0>;
|
|
hba-port-cap = <HBA_PORT_FBSCP>;
|
|
phys = <&combphy1_ps PHY_TYPE_SATA>;
|
|
phy-names = "sata-phy";
|
|
snps,rx-ts-max = <32>;
|
|
snps,tx-ts-max = <32>;
|
|
};
|
|
};
|
|
|
|
usbdp_phy1: phy@fed90000 {
|
|
compatible = "rockchip,rk3588-usbdp-phy";
|
|
reg = <0x0 0xfed90000 0x0 0x10000>;
|
|
#phy-cells = <1>;
|
|
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
|
<&cru PCLK_USBDPPHY1>,
|
|
<&u2phy1>;
|
|
clock-names = "refclk", "immortal", "pclk", "utmi";
|
|
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
|
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
|
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
|
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
|
<&cru SRST_P_USBDPPHY1>;
|
|
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
|
rockchip,usb-grf = <&usb_grf>;
|
|
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
|
rockchip,vo-grf = <&vo0_grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
combphy1_ps: phy@fee10000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee10000 0x0 0x100>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
|
<&cru PCLK_PHP_ROOT>;
|
|
clock-names = "ref", "apb", "pipe";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
|
assigned-clock-rates = <100000000>;
|
|
#phy-cells = <1>;
|
|
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
|
reset-names = "phy", "apb";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie30phy: phy@fee80000 {
|
|
compatible = "rockchip,rk3588-pcie3-phy";
|
|
reg = <0x0 0xfee80000 0x0 0x20000>;
|
|
#phy-cells = <0>;
|
|
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
|
clock-names = "pclk";
|
|
resets = <&cru SRST_PCIE30_PHY>;
|
|
reset-names = "phy";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
rockchip,phy-grf = <&pcie30_phy_grf>;
|
|
status = "disabled";
|
|
};
|
|
};
|