7d1163fc08
Commitda92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") enabled the mmu600_pcie IOMMU, both in the normal case (when all PCIe controllers are running in Root Complex mode) and in the case when running the pcie3x4 PCIe controller in Endpoint mode. There have been no issues detected when running the PCIe controllers in Root Complex mode. During PCI probe time, we will add a SID to the IOMMU for each PCI device enumerated on the bus, including the root port itself. However, when running the pcie3x4 PCIe controller in Endpoint mode, we will only add a single SID to the IOMMU (the SID specified in the iommus DT property). The enablement of IOMMU in endpoint mode was verified on setup with two Rock 5b:s, where the BDF of the Root Complex has BDF (00:00.0). A Root Complex sending a TLP to the Endpoint will have Requester ID set to the BDF of the initiator. On the EP side, the Requester ID will then be used as the SID. This works fine if the Root Complex has a BDF that matches the iommus DT property, however, if the Root Complex has any other BDF, we will see something like: arm-smmu-v3 fc900000.iommu: event: C_BAD_STREAMID client: (unassigned sid) sid: 0x1600 ssid: 0x0 on the endpoint side. For PCIe controllers running in endpoint mode that always uses the incoming Requester ID as the SID, the iommus DT property simply isn't a viable solution. (Neither is iommu-map a viable solution, as there is no enumeration done on the endpoint side.) Thus, partly revert commitda92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") by disabling the PCI IOMMU when running the pcie3x4 PCIe controller in Endpoint mode. Since the PCI IOMMU is working as expected in the normal case, keep it enabled when running all PCIe controllers in Root Complex mode. Fixes:da92d3dfc8("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC") Signed-off-by: Niklas Cassel <cassel@kernel.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20250207143900.2047949-2-cassel@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
29 lines
620 B
Text
29 lines
620 B
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
|
|
* in the SRNS (Separate Reference Clock No Spread) configuration.
|
|
*
|
|
* NOTE: If using a setup with two ROCK 5B:s, with one board running in
|
|
* RC mode and the other board running in EP mode, see also the device
|
|
* tree overlay: rk3588-rock-5b-pcie-srns.dtso.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
/plugin/;
|
|
|
|
&pcie30phy {
|
|
rockchip,rx-common-refclk-mode = <0 0 0 0>;
|
|
};
|
|
|
|
&pcie3x4 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie3x4_ep {
|
|
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
|
status = "okay";
|
|
};
|
|
|
|
&mmu600_pcie {
|
|
status = "disabled";
|
|
};
|