6b72cd9ef0
The notifier hook mechanism in proc and cpuinfo is actually unnecessary
for LoongArch because it's not used anywhere.
It was originally added to the MIPS code in commit d6d3c9afaa ("MIPS:
MT: proc: Add support for printing VPE and TC ids"), and LoongArch then
inherited it.
But as the kernel code stands now, this notifier hook mechanism doesn't
really make sense for either LoongArch or MIPS.
In addition, the seq_file forward declaration needs to be moved to its
proper place, as only the show_ipi_list() function in smp.c requires it.
Co-developed-by: Wentao Guan <guanwentao@uniontech.com>
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
Signed-off-by: Yuli Wang <wangyuli@uniontech.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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#include <linux/cache.h>
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#include <linux/types.h>
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#include <asm/loongarch.h>
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/* cache_desc->flags */
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enum {
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CACHE_PRESENT = (1 << 0),
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CACHE_PRIVATE = (1 << 1), /* core private cache */
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CACHE_INCLUSIVE = (1 << 2), /* include the inner level caches */
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};
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned char type;
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unsigned char level;
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unsigned short sets; /* Number of lines per set */
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unsigned char ways; /* Number of ways */
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unsigned char linesz; /* Size of line in bytes */
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unsigned char flags; /* Flags describing cache properties */
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};
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#define CACHE_LEVEL_MAX 3
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#define CACHE_LEAVES_MAX 6
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struct cpuinfo_loongarch {
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u64 asid_cache;
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unsigned long asid_mask;
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/*
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* Capability and feature descriptor structure for LoongArch CPU
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*/
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unsigned long long options;
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unsigned int processor_id;
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unsigned int fpu_vers;
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unsigned int fpu_csr0;
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unsigned int fpu_mask;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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int tlbsizemtlb;
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int tlbsizestlbsets;
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int tlbsizestlbways;
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int cache_leaves_present; /* number of cache_leaves[] elements */
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struct cache_desc cache_leaves[CACHE_LEAVES_MAX];
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int core; /* physical core number in package */
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int package;/* physical package number */
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int global_id; /* physical global thread number */
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int vabits; /* Virtual Address size in bits */
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int pabits; /* Physical Address size in bits */
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int timerbits; /* Width of arch timer in bits */
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unsigned int ksave_mask; /* Usable KSave mask. */
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unsigned int watch_dreg_count; /* Number data breakpoints */
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unsigned int watch_ireg_count; /* Number instruction breakpoints */
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unsigned int watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
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} __aligned(SMP_CACHE_BYTES);
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extern struct cpuinfo_loongarch cpu_data[];
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#define boot_cpu_data cpu_data[0]
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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extern void cpu_probe(void);
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extern const char *__cpu_family[];
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extern const char *__cpu_full_name[];
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#define cpu_family_string() __cpu_family[raw_smp_processor_id()]
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#define cpu_full_name_string() __cpu_full_name[raw_smp_processor_id()]
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static inline bool cpus_are_siblings(int cpua, int cpub)
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{
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struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
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struct cpuinfo_loongarch *infob = &cpu_data[cpub];
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if (infoa->package != infob->package)
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return false;
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if (infoa->core != infob->core)
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return false;
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return true;
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}
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static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
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{
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return cpuinfo->asid_mask;
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}
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static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
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unsigned long asid_mask)
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{
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cpuinfo->asid_mask = asid_mask;
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}
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#endif /* __ASM_CPU_INFO_H */
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