edb1942542
LoongArch re-enables interrupts on its idle routine and performs a
TIF_NEED_RESCHED check afterwards before putting the CPU to sleep.
The IRQs firing between the check and the idle instruction may set the
TIF_NEED_RESCHED flag. In order to deal with such a race, IRQs
interrupting __arch_cpu_idle() rollback their return address to the
beginning of __arch_cpu_idle() so that TIF_NEED_RESCHED is checked
again before going back to sleep.
However idle IRQs can also queue timers that may require a tick
reprogramming through a new generic idle loop iteration but those timers
would go unnoticed here because __arch_cpu_idle() only checks
TIF_NEED_RESCHED. It doesn't check for pending timers.
Fix this with fast-forwarding idle IRQs return address to the end of the
idle routine instead of the beginning, so that the generic idle loop can
handle both TIF_NEED_RESCHED and pending timers.
Fixes: 0603839b18 ("LoongArch: Add exception/interrupt handling")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Frederic Weisbecker <frederic@kernel.org>
Signed-off-by: Marco Crivellari <marco.crivellari@suse.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
107 lines
2.6 KiB
ArmAsm
107 lines
2.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2002, 2007 Maciej W. Rozycki
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* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/loongarch.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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.align 5
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SYM_FUNC_START(__arch_cpu_idle)
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/* start of idle interrupt region */
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ori t0, zero, CSR_CRMD_IE
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/* idle instruction needs irq enabled */
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csrxchg t0, t0, LOONGARCH_CSR_CRMD
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/*
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* If an interrupt lands here; between enabling interrupts above and
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* going idle on the next instruction, we must *NOT* go idle since the
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* interrupt could have set TIF_NEED_RESCHED or caused an timer to need
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* reprogramming. Fall through -- see handle_vint() below -- and have
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* the idle loop take care of things.
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*/
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idle 0
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/* end of idle interrupt region */
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1: jr ra
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SYM_FUNC_END(__arch_cpu_idle)
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SYM_CODE_START(handle_vint)
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UNWIND_HINT_UNDEFINED
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BACKUP_T0T1
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SAVE_ALL
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la_abs t1, 1b
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LONG_L t0, sp, PT_ERA
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/* 3 instructions idle interrupt region */
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ori t0, t0, 0b1100
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bne t0, t1, 1f
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LONG_S t0, sp, PT_ERA
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1: move a0, sp
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move a1, sp
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la_abs t0, do_vint
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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SYM_CODE_END(handle_vint)
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SYM_CODE_START(except_vec_cex)
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UNWIND_HINT_UNDEFINED
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b cache_parity_error
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SYM_CODE_END(except_vec_cex)
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.macro build_prep_badv
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csrrd t0, LOONGARCH_CSR_BADV
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PTR_S t0, sp, PT_BVADDR
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.endm
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.macro build_prep_fcsr
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movfcsr2gr a1, fcsr0
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.endm
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.macro build_prep_none
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.endm
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.macro BUILD_HANDLER exception handler prep
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.align 5
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SYM_CODE_START(handle_\exception)
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UNWIND_HINT_UNDEFINED
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666:
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BACKUP_T0T1
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SAVE_ALL
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build_prep_\prep
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move a0, sp
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la_abs t0, do_\handler
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jirl ra, t0, 0
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668:
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RESTORE_ALL_AND_RET
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SYM_CODE_END(handle_\exception)
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.pushsection ".data", "aw", %progbits
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SYM_DATA(unwind_hint_\exception, .word 668b - 666b)
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.popsection
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.endm
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BUILD_HANDLER ade ade badv
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BUILD_HANDLER ale ale badv
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BUILD_HANDLER bce bce none
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BUILD_HANDLER bp bp none
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BUILD_HANDLER fpe fpe fcsr
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BUILD_HANDLER fpu fpu none
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BUILD_HANDLER lsx lsx none
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BUILD_HANDLER lasx lasx none
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BUILD_HANDLER lbt lbt none
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BUILD_HANDLER ri ri none
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BUILD_HANDLER watch watch none
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BUILD_HANDLER reserved reserved none /* others */
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SYM_CODE_START(handle_sys)
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UNWIND_HINT_UNDEFINED
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la_abs t0, handle_syscall
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jr t0
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SYM_CODE_END(handle_sys)
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