61bcc752d1
Rewrite __real_pte() and __rpte_to_hidx() as static inline in order to
avoid following warnings/errors when building with 4k page size:
CC arch/powerpc/mm/book3s64/hash_tlb.o
arch/powerpc/mm/book3s64/hash_tlb.c: In function 'hpte_need_flush':
arch/powerpc/mm/book3s64/hash_tlb.c:49:16: error: variable 'offset' set but not used [-Werror=unused-but-set-variable]
49 | int i, offset;
| ^~~~~~
CC arch/powerpc/mm/book3s64/hash_native.o
arch/powerpc/mm/book3s64/hash_native.c: In function 'native_flush_hash_range':
arch/powerpc/mm/book3s64/hash_native.c:782:29: error: variable 'index' set but not used [-Werror=unused-but-set-variable]
782 | unsigned long hash, index, hidx, shift, slot;
| ^~~~~
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202501081741.AYFwybsq-lkp@intel.com/
Fixes: ff31e10546 ("powerpc/mm/hash64: Store the slot information at the right offset for hugetlb")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/e0d340a5b7bd478ecbf245d826e6ab2778b74e06.1736706263.git.christophe.leroy@csgroup.eu
179 lines
5.2 KiB
C
179 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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#define H_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 4KB = 2MB
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#define H_PMD_INDEX_SIZE 7 // size: 8B << 7 = 1KB, maps: 2^7 x 2MB = 256MB
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#define H_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
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#define H_PGD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 128GB = 64TB
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/*
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* Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
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* Hence also limit max EA bits to 64TB.
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*/
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#define MAX_EA_BITS_PER_CONTEXT 46
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/*
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* Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
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* of vmemmap space. To better support sparse memory layout, we use 61TB
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* linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap.
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*/
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#define REGION_SHIFT (40)
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#define H_KERN_MAP_SIZE (ASM_CONST(1) << REGION_SHIFT)
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/*
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* Limits the linear mapping range
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*/
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#define H_MAX_PHYSMEM_BITS 46
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/*
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* Define the address range of the kernel non-linear virtual area (61TB)
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*/
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#define H_KERN_VIRT_START ASM_CONST(0xc0003d0000000000)
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#ifndef __ASSEMBLY__
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#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
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#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
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#define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
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#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
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#define H_PAGE_F_GIX_SHIFT _PAGE_PA_MAX
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#define H_PAGE_F_SECOND _RPAGE_PKEY_BIT0 /* HPTE is in 2ndary HPTEG */
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#define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
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#define H_PAGE_BUSY _RPAGE_RSV1
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#define H_PAGE_HASHPTE _RPAGE_PKEY_BIT4
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
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H_PAGE_F_SECOND | H_PAGE_F_GIX)
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/*
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* Not supported by 4k linux page size
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*/
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#define H_PAGE_4K_PFN 0x0
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#define H_PAGE_THP_HUGE 0x0
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#define H_PAGE_COMBO 0x0
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/* 8 bytes per each pte entry */
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#define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3)
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#define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
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#define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3)
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#define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
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/* memory key bits, only 8 keys supported */
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#define H_PTE_PKEY_BIT4 0
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#define H_PTE_PKEY_BIT3 0
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#define H_PTE_PKEY_BIT2 _RPAGE_PKEY_BIT3
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#define H_PTE_PKEY_BIT1 _RPAGE_PKEY_BIT2
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#define H_PTE_PKEY_BIT0 _RPAGE_PKEY_BIT1
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/*
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* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
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*/
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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/*
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* With 4K page size the real_pte machinery is all nops.
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*/
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static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
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{
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return (real_pte_t){pte};
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}
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#define __rpte_to_pte(r) ((r).pte)
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static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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{
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return pte_val(__rpte_to_pte(rpte)) >> H_PAGE_F_GIX_SHIFT;
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}
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#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
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do { \
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index = 0; \
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shift = mmu_psize_defs[psize].shift; \
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#define pte_iterate_hashed_end() } while(0)
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/*
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* We expect this to be called only for user addresses or kernel virtual
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* addresses other than the linear mapping.
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*/
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#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
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/*
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* 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
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* a matter of returning the PTE bits that need to be modified. On 64K PTE,
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* things are a little more involved and hence needs many more parameters to
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* accomplish the same. However we want to abstract this out from the caller by
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* keeping the prototype consistent across the two formats.
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*/
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static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
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unsigned int subpg_index, unsigned long hidx,
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int offset)
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{
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return (hidx << H_PAGE_F_GIX_SHIFT) &
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(H_PAGE_F_SECOND | H_PAGE_F_GIX);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static inline char *get_hpte_slot_array(pmd_t *pmdp)
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{
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BUG();
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return NULL;
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}
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static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
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{
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BUG();
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return 0;
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}
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static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
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int index)
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{
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BUG();
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return 0;
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}
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static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
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unsigned int index, unsigned int hidx)
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{
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BUG();
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}
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static inline int hash__pmd_trans_huge(pmd_t pmd)
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{
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return 0;
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}
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static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
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{
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BUG();
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return pmd;
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}
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extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp,
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unsigned long clr, unsigned long set);
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extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable);
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extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
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extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp);
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extern int hash__has_transparent_hugepage(void);
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#endif
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static inline pmd_t hash__pmd_mkdevmap(pmd_t pmd)
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{
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BUG();
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return pmd;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
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