Eric Yang 133e8e1b35 drm/amd/display: Change how we disable pipe split ... Before this change, pipe split was disabled by bumping up dpp clock bounding box for DPM level 0 and 1, this allows validation to pass without splitting at a lower DPM level. This change reverts this and instead lowers display clock at DPM level 0, this forces configurations that need pipe split at DPM level 0 to go to DPM level 1, where they can be driven without split. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-09-26 18:08:40 -04:00
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drm	drm/amd/display: Change how we disable pipe split	2017-09-26 18:08:40 -04:00
host1x	drm/tegra: Changes for v4.14-rc1	2017-08-21 17:37:33 +10:00
ipu-v3	drm: Convert to using %pOF instead of full_name	2017-07-26 13:45:06 +02:00
vga	sched/wait: Rename wait_queue_t => wait_queue_entry_t	2017-06-20 12:18:27 +02:00
Makefile