b87d390196
As with EU masks, it's easier to store subslice/DSS masks internally in a format that's more natural for the driver to work with, and then only covert into the u8[] uapi form when the query ioctl is invoked. Since the hardware design changed significantly with Xe_HP, we'll use a union to choose between the old "hsw-style" subslice masks or the newer xehp mask. HSW-style masks will be stored in an array of u8's, indexed by slice (there's never more than 6 subslices per slice on older platforms). For Xe_HP and beyond where slices no longer exist, we only need a single bitmask. However we already know that this mask is eventually going to grow too large for a simple u64 to hold, so we'll represent it in a manner that can be operated on by the utilities in linux/bitmap.h. v2: - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status() v3: - Eliminate sseu->ss_stride and just calculate the stride while specifically handling uapi. (Tvrtko) - Use BITMAP_BITS() macro to refer to size of masks rather than passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko) - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU info. (Tvrtko) - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko) v4: - Make the bitmap size macro check the size of the .xehp field rather than the containing union. (Tvrtko) - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether slice or subslice ID exceed sseu->max_[sub]slices; various loops in the driver are expected to exceed these, so we should just silently return 'false.' v5: - Move XEHP_BITMAP_BITS() to the header so that we can also replace a usage of I915_MAX_SS_FUSE_BITS in one of the inline functions. (Bala) - Change the local variable in intel_slicemask_from_xehp_dssmask() from u16 to 'unsigned long' to make it a bit more future-proof. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-6-matthew.d.roper@intel.com
187 lines
5.1 KiB
C
187 lines
5.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*/
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#include "gem/i915_gem_mman.h"
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#include "gt/intel_engine_user.h"
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#include "i915_cmd_parser.h"
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#include "i915_drv.h"
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#include "i915_getparam.h"
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#include "i915_perf.h"
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int i915_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_i915_private *i915 = to_i915(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
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drm_i915_getparam_t *param = data;
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int value = 0;
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switch (param->param) {
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case I915_PARAM_IRQ_ACTIVE:
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case I915_PARAM_ALLOW_BATCHBUFFER:
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case I915_PARAM_LAST_DISPATCH:
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case I915_PARAM_HAS_EXEC_CONSTANTS:
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/* Reject all old ums/dri params. */
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return -ENODEV;
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case I915_PARAM_CHIPSET_ID:
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value = pdev->device;
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break;
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case I915_PARAM_REVISION:
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value = pdev->revision;
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break;
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case I915_PARAM_NUM_FENCES_AVAIL:
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value = to_gt(i915)->ggtt->num_fences;
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break;
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case I915_PARAM_HAS_OVERLAY:
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value = !!i915->overlay;
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break;
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case I915_PARAM_HAS_BSD:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 0);
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break;
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case I915_PARAM_HAS_BLT:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_COPY, 0);
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break;
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case I915_PARAM_HAS_VEBOX:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
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break;
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case I915_PARAM_HAS_BSD2:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 1);
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break;
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case I915_PARAM_HAS_LLC:
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value = HAS_LLC(i915);
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break;
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case I915_PARAM_HAS_WT:
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value = HAS_WT(i915);
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break;
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case I915_PARAM_HAS_ALIASING_PPGTT:
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value = INTEL_PPGTT(i915);
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break;
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case I915_PARAM_HAS_SEMAPHORES:
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value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
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break;
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case I915_PARAM_HAS_SECURE_BATCHES:
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value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
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break;
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case I915_PARAM_CMD_PARSER_VERSION:
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value = i915_cmd_parser_get_version(i915);
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break;
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case I915_PARAM_SUBSLICE_TOTAL:
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value = intel_sseu_subslice_total(sseu);
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_EU_TOTAL:
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value = sseu->eu_total;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_HAS_GPU_RESET:
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value = i915->params.enable_hangcheck &&
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intel_has_gpu_reset(to_gt(i915));
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if (value && intel_has_reset_engine(to_gt(i915)))
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value = 2;
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break;
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case I915_PARAM_HAS_RESOURCE_STREAMER:
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value = 0;
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break;
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case I915_PARAM_HAS_POOLED_EU:
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value = HAS_POOLED_EU(i915);
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break;
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case I915_PARAM_MIN_EU_IN_POOL:
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value = sseu->min_eu_in_pool;
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break;
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case I915_PARAM_HUC_STATUS:
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value = intel_huc_check_status(&to_gt(i915)->uc.huc);
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if (value < 0)
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return value;
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break;
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case I915_PARAM_MMAP_GTT_VERSION:
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/* Though we've started our numbering from 1, and so class all
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* earlier versions as 0, in effect their value is undefined as
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* the ioctl will report EINVAL for the unknown param!
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*/
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value = i915_gem_mmap_gtt_version();
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break;
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case I915_PARAM_HAS_SCHEDULER:
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value = i915->caps.scheduler;
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break;
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case I915_PARAM_MMAP_VERSION:
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/* Remember to bump this if the version changes! */
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case I915_PARAM_HAS_GEM:
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case I915_PARAM_HAS_PAGEFLIPPING:
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case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
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case I915_PARAM_HAS_RELAXED_FENCING:
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case I915_PARAM_HAS_COHERENT_RINGS:
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case I915_PARAM_HAS_RELAXED_DELTA:
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case I915_PARAM_HAS_GEN7_SOL_RESET:
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case I915_PARAM_HAS_WAIT_TIMEOUT:
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case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
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case I915_PARAM_HAS_PINNED_BATCHES:
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case I915_PARAM_HAS_EXEC_NO_RELOC:
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case I915_PARAM_HAS_EXEC_HANDLE_LUT:
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case I915_PARAM_HAS_COHERENT_PHYS_GTT:
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case I915_PARAM_HAS_EXEC_SOFTPIN:
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case I915_PARAM_HAS_EXEC_ASYNC:
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case I915_PARAM_HAS_EXEC_FENCE:
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case I915_PARAM_HAS_EXEC_CAPTURE:
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case I915_PARAM_HAS_EXEC_BATCH_FIRST:
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case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
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case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
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case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
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case I915_PARAM_HAS_USERPTR_PROBE:
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/* For the time being all of these are always true;
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* if some supported hardware does not have one of these
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* features this value needs to be provided from
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* INTEL_INFO(), a feature macro, or similar.
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*/
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value = 1;
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break;
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case I915_PARAM_HAS_CONTEXT_ISOLATION:
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value = intel_engines_has_context_isolation(i915);
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break;
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case I915_PARAM_SLICE_MASK:
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/* Not supported from Xe_HP onward; use topology queries */
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
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return -EINVAL;
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value = sseu->slice_mask;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_SUBSLICE_MASK:
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/* Not supported from Xe_HP onward; use topology queries */
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
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return -EINVAL;
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/* Only copy bits from the first slice */
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value = intel_sseu_get_hsw_subslices(sseu, 0);
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
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value = to_gt(i915)->clock_frequency;
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break;
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case I915_PARAM_MMAP_GTT_COHERENT:
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value = INTEL_INFO(i915)->has_coherent_ggtt;
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break;
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case I915_PARAM_PERF_REVISION:
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value = i915_perf_ioctl_version();
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break;
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default:
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DRM_DEBUG("Unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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if (put_user(value, param->value))
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return -EFAULT;
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return 0;
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}
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