df57721f9a
Convert IBT selftest to asm to fix objtool warning -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEV76QKkVc4xCGURexaDWVMHDJkrAFAmTv1QQACgkQaDWVMHDJ krAUwhAAn6TOwHJK8BSkHeiQhON1nrlP3c5cv0AyZ2NP8RYDrZrSZvhpYBJ6wgKC Cx5CGq5nn9twYsYS3KsktLKDfR3lRdsQ7K9qtyFtYiaeaVKo+7gEKl/K+klwai8/ gninQWHk0zmSCja8Vi77q52WOMkQKapT8+vaON9EVDO8dVEi+CvhAIfPwMafuiwO Rk4X86SzoZu9FP79LcCg9XyGC/XbM2OG9eNUTSCKT40qTTKm5y4gix687NvAlaHR ko5MTsdl0Wfp6Qk0ohT74LnoA2c1g/FluvZIM33ci/2rFpkf9Hw7ip3lUXqn6CPx rKiZ+pVRc0xikVWkraMfIGMJfUd2rhelp8OyoozD7DB7UZw40Q4RW4N5tgq9Fhe9 MQs3p1v9N8xHdRKl365UcOczUxNAmv4u0nV5gY/4FMC6VjldCl2V9fmqYXyzFS4/ Ogg4FSd7c2JyGFKPs+5uXyi+RY2qOX4+nzHOoKD7SY616IYqtgKoz5usxETLwZ6s VtJOmJL0h//z0A7tBliB0zd+SQ5UQQBDC2XouQH2fNX2isJMn0UDmWJGjaHgK6Hh 8jVp6LNqf+CEQS387UxckOyj7fu438hDky1Ggaw4YqowEOhQeqLVO4++x+HITrbp AupXfbJw9h9cMN63Yc0gVxXQ9IMZ+M7UxLtZ3Cd8/PVztNy/clA= =3UUm -----END PGP SIGNATURE----- Merge tag 'x86_shstk_for_6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 shadow stack support from Dave Hansen: "This is the long awaited x86 shadow stack support, part of Intel's Control-flow Enforcement Technology (CET). CET consists of two related security features: shadow stacks and indirect branch tracking. This series implements just the shadow stack part of this feature, and just for userspace. The main use case for shadow stack is providing protection against return oriented programming attacks. It works by maintaining a secondary (shadow) stack using a special memory type that has protections against modification. When executing a CALL instruction, the processor pushes the return address to both the normal stack and to the special permission shadow stack. Upon RET, the processor pops the shadow stack copy and compares it to the normal stack copy. For more information, refer to the links below for the earlier versions of this patch set" Link: https://lore.kernel.org/lkml/20220130211838.8382-1-rick.p.edgecombe@intel.com/ Link: https://lore.kernel.org/lkml/20230613001108.3040476-1-rick.p.edgecombe@intel.com/ * tag 'x86_shstk_for_6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (47 commits) x86/shstk: Change order of __user in type x86/ibt: Convert IBT selftest to asm x86/shstk: Don't retry vm_munmap() on -EINTR x86/kbuild: Fix Documentation/ reference x86/shstk: Move arch detail comment out of core mm x86/shstk: Add ARCH_SHSTK_STATUS x86/shstk: Add ARCH_SHSTK_UNLOCK x86: Add PTRACE interface for shadow stack selftests/x86: Add shadow stack test x86/cpufeatures: Enable CET CR4 bit for shadow stack x86/shstk: Wire in shadow stack interface x86: Expose thread features in /proc/$PID/status x86/shstk: Support WRSS for userspace x86/shstk: Introduce map_shadow_stack syscall x86/shstk: Check that signal frame is shadow stack mem x86/shstk: Check that SSP is aligned on sigreturn x86/shstk: Handle signals for shadow stack x86/shstk: Introduce routines modifying shstk x86/shstk: Handle thread shadow stack x86/shstk: Add user-mode shadow stack support ...
334 lines
10 KiB
C
334 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/pgtable.h
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*
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* Copyright (C) 1995-2002 Russell King
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*/
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#ifndef _ASMARM_PGTABLE_H
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#define _ASMARM_PGTABLE_H
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#include <linux/const.h>
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#include <asm/proc-fns.h>
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#ifndef __ASSEMBLY__
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern struct page *empty_zero_page;
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#define ZERO_PAGE(vaddr) (empty_zero_page)
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#endif
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#ifndef CONFIG_MMU
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#include <asm-generic/pgtable-nopud.h>
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#include <asm/pgtable-nommu.h>
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#else
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#include <asm-generic/pgtable-nopud.h>
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#include <asm/page.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_ARM_LPAE
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#include <asm/pgtable-3level.h>
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#else
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#include <asm/pgtable-2level.h>
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#endif
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/*
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* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*/
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#define VMALLOC_OFFSET (8*1024*1024)
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#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
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#define VMALLOC_END 0xff800000UL
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#define LIBRARY_TEXT_START 0x0c000000
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#ifndef __ASSEMBLY__
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extern void __pte_error(const char *file, int line, pte_t);
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extern void __pmd_error(const char *file, int line, pmd_t);
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extern void __pgd_error(const char *file, int line, pgd_t);
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#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
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#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
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#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
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/*
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* This is the lowest virtual address we can permit any user space
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* mapping to be mapped at. This is particularly important for
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* non-high vector CPUs.
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*/
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#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
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/*
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* Use TASK_SIZE as the ceiling argument for free_pgtables() and
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* free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
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* page shared between user and kernel).
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*/
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#ifdef CONFIG_ARM_LPAE
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#define USER_PGTABLES_CEILING TASK_SIZE
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#endif
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/*
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* The pgprot_* and protection_map entries will be fixed up in runtime
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* to include the cachable and bufferable bits based on memory policy,
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* as well as any architecture dependent bits like global/ASID and SMP
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* shared mapping bits.
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*/
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#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
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extern pgprot_t pgprot_user;
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extern pgprot_t pgprot_kernel;
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#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
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#define PAGE_NONE _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
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#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
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#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER)
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#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
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#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
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#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
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#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
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#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
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#define PAGE_KERNEL_EXEC pgprot_kernel
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#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
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#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
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#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
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#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
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#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
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#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
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#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
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#define __pgprot_modify(prot,mask,bits) \
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__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
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#define pgprot_noncached(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
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#define pgprot_writecombine(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
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#define pgprot_stronglyordered(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#else
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
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#endif
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#endif /* __ASSEMBLY__ */
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/*
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* The table below defines the page protection levels that we insert into our
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* Linux page table version. These get translated into the best that the
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* architecture can perform. Note that on most ARM hardware:
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* 1) We cannot do execute protection
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* 2) If we could do execute protection, then read is implied
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* 3) write implies read permissions
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*/
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#ifndef __ASSEMBLY__
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
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#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
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#define pmd_none(pmd) (!pmd_val(pmd))
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static inline pte_t *pmd_page_vaddr(pmd_t pmd)
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{
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return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
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}
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#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
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#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
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#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
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#define pte_page(pte) pfn_to_page(pte_pfn(pte))
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#define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot)
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#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
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#define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \
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: !!(pte_val(pte) & (val)))
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#define pte_isclear(pte, val) (!(pte_val(pte) & (val)))
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#define pte_none(pte) (!pte_val(pte))
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#define pte_present(pte) (pte_isset((pte), L_PTE_PRESENT))
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#define pte_valid(pte) (pte_isset((pte), L_PTE_VALID))
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#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
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#define pte_write(pte) (pte_isclear((pte), L_PTE_RDONLY))
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#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
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#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
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#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
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#define pte_valid_user(pte) \
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(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
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static inline bool pte_access_permitted(pte_t pte, bool write)
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{
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pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
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pteval_t needed = mask;
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if (write)
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mask |= L_PTE_RDONLY;
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return (pte_val(pte) & mask) == needed;
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}
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#define pte_access_permitted pte_access_permitted
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#if __LINUX_ARM_ARCH__ < 6
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static inline void __sync_icache_dcache(pte_t pteval)
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{
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}
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#else
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extern void __sync_icache_dcache(pte_t pteval);
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#endif
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void set_ptes(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pteval, unsigned int nr);
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#define set_ptes set_ptes
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static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
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{
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pte_val(pte) &= ~pgprot_val(prot);
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return pte;
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}
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static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
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{
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pte_val(pte) |= pgprot_val(prot);
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return pte;
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}
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
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}
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static inline pte_t pte_mkwrite_novma(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
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}
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static inline pte_t pte_mkexec(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(L_PTE_XN));
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}
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static inline pte_t pte_mknexec(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(L_PTE_XN));
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}
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
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L_PTE_NONE | L_PTE_VALID;
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pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
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return pte;
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}
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/*
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
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* are !pte_none() && !pte_present().
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*
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* Format of swap PTEs:
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* <------------------- offset ------------------> E < type -> 0 0
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*
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* E is the exclusive marker that is not stored in swap entries.
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*
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* This gives us up to 31 swap files and 64GB per swap file. Note that
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* the offset field is always non-zero.
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*/
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#define __SWP_TYPE_SHIFT 2
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#define __SWP_TYPE_BITS 5
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#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
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#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
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#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
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#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
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((offset) << __SWP_OFFSET_SHIFT) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(swp) __pte((swp).val)
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static inline int pte_swp_exclusive(pte_t pte)
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{
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return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
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}
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static inline pte_t pte_swp_mkexclusive(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
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}
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static inline pte_t pte_swp_clear_exclusive(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
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}
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/*
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* It is an error for the kernel to have more swap files than we can
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* encode in the PTEs. This ensures that we know when MAX_SWAPFILES
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* is increased beyond what we presently support.
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*/
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
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/*
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* We provide our own arch_get_unmapped_area to cope with VIPT caches.
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*/
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#endif /* !__ASSEMBLY__ */
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#endif /* CONFIG_MMU */
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#endif /* _ASMARM_PGTABLE_H */
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