56d428ae1c
* Support for handling misaligned accesses in S-mode. * Probing for misaligned access support is now properly cached and handled in parallel. * PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions. * Performance improvements for TLB flushing. * Support for many new relocations in the module loader. * Various bug fixes and cleanups. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVOUCcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYicJ2D/9S+9dnHYHVGTeJfr9Zf2T4r+qHBPyx LXbTAbgHN6139MgcRLMRlcUaQ04RVxuBCWhxewJ6mQiHiYNlullgKmJO8oYMS4uZ 2yQGHKhzKEVluXxe+qT6VW+zsP0cY6pDQ+e59AqZgyWzvATxMU4VtFfCDdjFG03I k/8Y3MUKSHAKzIHUsGHiMW5J2YRiM/iVehv2gZfanreulWlK6lyiV4AZ4KChu8Sa gix9QkFJw+9+7RHnouHvczt4xTqLPJQcdecLJsbisEI4VaaPtTVzkvXx/kwbMwX0 qkQnZ7I60fPHrCb9ccuedjDMa1Z0lrfwRldBGz9f9QaW37Eppirn6LA5JiZ1cA47 wKTwba6gZJCTRXELFTJLcv+Cwdy003E0y3iL5UK2rkbLqcxfvLdq1WAJU2t05Lmh aRQN10BtM2DZG+SNPlLoBpXPDw0Q3KOc20zGtuhmk010+X4yOK7WXlu8zNGLLE0+ yHamiZqAbpIUIEzwDdGbb95jywR1sUhNTbScuhj4Rc79ZqLtPxty1PUhnfqFat1R i3ngQtCbeUUYFS2YV9tKkXjLf/xkQNRbt7kQBowuvFuvfksl9UwMdRAWcE/h0M9P 7uz7cBFhuG0v/XblB7bUhYLkKITvP+ltSMyxaGlfpGqCLAH2KIztdZ2PLWLRdKeU +9dtZSQR6oBLqQ== =NhdR -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for handling misaligned accesses in S-mode - Probing for misaligned access support is now properly cached and handled in parallel - PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions - Performance improvements for TLB flushing - Support for many new relocations in the module loader - Various bug fixes and cleanups * tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) riscv: Optimize bitops with Zbb extension riscv: Rearrange hwcap.h and cpufeature.h drivers: perf: Do not broadcast to other cpus when starting a counter drivers: perf: Check find_first_bit() return value of: property: Add fw_devlink support for msi-parent RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings riscv: Don't use PGD entries for the linear mapping RISC-V: Probe misaligned access speed in parallel RISC-V: Remove __init on unaligned_emulation_finish() RISC-V: Show accurate per-hart isa in /proc/cpuinfo RISC-V: Don't rely on positional structure initialization riscv: Add tests for riscv module loading riscv: Add remaining module relocations riscv: Avoid unaligned access when relocating modules riscv: split cache ops out of dma-noncoherent.c riscv: Improve flush_tlb_kernel_range() riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: Improve flush_tlb_range() for hugetlb pages riscv: Improve tlb_flush() ...
150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_PROCESSOR_H
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#define _ASM_RISCV_PROCESSOR_H
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#include <linux/const.h>
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#include <linux/cache.h>
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#include <linux/prctl.h>
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#include <vdso/processor.h>
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#include <asm/ptrace.h>
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#ifdef CONFIG_64BIT
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#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
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#define STACK_TOP_MAX TASK_SIZE_64
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#define arch_get_mmap_end(addr, len, flags) \
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({ \
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unsigned long mmap_end; \
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typeof(addr) _addr = (addr); \
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if ((_addr) == 0 || (IS_ENABLED(CONFIG_COMPAT) && is_compat_task())) \
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mmap_end = STACK_TOP_MAX; \
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else if ((_addr) >= VA_USER_SV57) \
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mmap_end = STACK_TOP_MAX; \
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else if ((((_addr) >= VA_USER_SV48)) && (VA_BITS >= VA_BITS_SV48)) \
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mmap_end = VA_USER_SV48; \
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else \
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mmap_end = VA_USER_SV39; \
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mmap_end; \
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})
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#define arch_get_mmap_base(addr, base) \
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({ \
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unsigned long mmap_base; \
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typeof(addr) _addr = (addr); \
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typeof(base) _base = (base); \
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unsigned long rnd_gap = DEFAULT_MAP_WINDOW - (_base); \
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if ((_addr) == 0 || (IS_ENABLED(CONFIG_COMPAT) && is_compat_task())) \
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mmap_base = (_base); \
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else if (((_addr) >= VA_USER_SV57) && (VA_BITS >= VA_BITS_SV57)) \
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mmap_base = VA_USER_SV57 - rnd_gap; \
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else if ((((_addr) >= VA_USER_SV48)) && (VA_BITS >= VA_BITS_SV48)) \
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mmap_base = VA_USER_SV48 - rnd_gap; \
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else \
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mmap_base = VA_USER_SV39 - rnd_gap; \
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mmap_base; \
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})
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#else
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#define DEFAULT_MAP_WINDOW TASK_SIZE
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#define STACK_TOP_MAX TASK_SIZE
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#endif
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#define STACK_ALIGN 16
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#define STACK_TOP DEFAULT_MAP_WINDOW
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/*
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* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#ifdef CONFIG_64BIT
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#define TASK_UNMAPPED_BASE PAGE_ALIGN((UL(1) << MMAP_MIN_VA_BITS) / 3)
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#else
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#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
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#endif
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#ifndef __ASSEMBLY__
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struct task_struct;
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struct pt_regs;
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/* CPU-specific state of a task */
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struct thread_struct {
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/* Callee-saved registers */
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unsigned long ra;
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unsigned long sp; /* Kernel mode stack */
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unsigned long s[12]; /* s[0]: frame pointer */
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struct __riscv_d_ext_state fstate;
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unsigned long bad_cause;
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unsigned long vstate_ctrl;
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struct __riscv_v_ext_state vstate;
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unsigned long align_ctl;
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};
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/* Whitelist the fstate from the task_struct for hardened usercopy */
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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unsigned long *size)
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{
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*offset = offsetof(struct thread_struct, fstate);
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*size = sizeof_field(struct thread_struct, fstate);
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}
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#define INIT_THREAD { \
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.sp = sizeof(init_stack) + (long)&init_stack, \
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.align_ctl = PR_UNALIGN_NOPRINT, \
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}
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#define task_pt_regs(tsk) \
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((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \
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- ALIGN(sizeof(struct pt_regs), STACK_ALIGN)))
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
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/* Do necessary setup to start up a newly executed thread. */
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extern void start_thread(struct pt_regs *regs,
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unsigned long pc, unsigned long sp);
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extern unsigned long __get_wchan(struct task_struct *p);
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static inline void wait_for_interrupt(void)
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{
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__asm__ __volatile__ ("wfi");
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}
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extern phys_addr_t dma32_phys_limit;
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struct device_node;
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int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
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int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
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int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
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extern void riscv_fill_hwcap(void);
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extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
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extern unsigned long signal_minsigstksz __ro_after_init;
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#ifdef CONFIG_RISCV_ISA_V
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/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
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#define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg)
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#define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current()
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extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
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extern long riscv_v_vstate_ctrl_get_current(void);
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#endif /* CONFIG_RISCV_ISA_V */
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extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr);
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extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
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#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
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#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_PROCESSOR_H */
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