e9603f4bdc
Sometimes QCA6390 doesn't switch to amss state as device enters L1ss state, so disable L0sL1s during firmware downloading. Driver recovers the ASPM to default value in start callback or powerdown callback. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1608218530-15426-1-git-send-email-kvalo@codeaurora.org
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _ATH11K_PCI_H
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#define _ATH11K_PCI_H
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#include <linux/mhi.h>
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#include "core.h"
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#define PCIE_SOC_GLOBAL_RESET 0x3008
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#define PCIE_SOC_GLOBAL_RESET_V 1
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#define WLAON_WARM_SW_ENTRY 0x1f80504
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#define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
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#define PCIE_Q6_COOKIE_ADDR 0x01f80500
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#define PCIE_Q6_COOKIE_DATA 0xc0000000
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/* register to wake the UMAC from power collapse */
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#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
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/* register used for handshake mechanism to validate UMAC is awake */
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#define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
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#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
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#define PARM_LTSSM_VALUE 0x111
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#define GCC_GCC_PCIE_HOT_RST 0x1e402bc
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#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
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#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
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#define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
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#define PCIE_INT_CLEAR_ALL 0xffffffff
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG 0x01e0c0ac
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_REG 0x01e0c628
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_VAL 0x02
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_REG 0x01e0c62c
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_VAL 0x52
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_REG 0x01e0c634
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_VAL 0xff
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#define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK 0x000000ff
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#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
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#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
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struct ath11k_msi_user {
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char *name;
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int num_vectors;
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u32 base_vector;
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};
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struct ath11k_msi_config {
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int total_vectors;
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int total_users;
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struct ath11k_msi_user *users;
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};
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enum ath11k_pci_flags {
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ATH11K_PCI_FLAG_INIT_DONE,
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ATH11K_PCI_FLAG_IS_MSI_64,
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ATH11K_PCI_ASPM_RESTORE,
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};
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struct ath11k_pci {
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struct pci_dev *pdev;
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struct ath11k_base *ab;
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u16 dev_id;
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char amss_path[100];
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u32 msi_ep_base_data;
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struct mhi_controller *mhi_ctrl;
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unsigned long mhi_state;
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u32 register_window;
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/* protects register_window above */
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spinlock_t window_lock;
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/* enum ath11k_pci_flags */
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unsigned long flags;
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u16 link_ctl;
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};
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static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
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{
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return (struct ath11k_pci *)ab->drv_priv;
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}
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int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
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int *num_vectors, u32 *user_base_data,
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u32 *base_vector);
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int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
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void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
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u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
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#endif
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