KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
rise enough to release the reset.
For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
VDDIO - VIH
t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
VDDIO
so we need ~95 ms for the reset to really de-assert, and then the
original 100us for the switch itself to come out of reset. Simply
msleep() for 100 ms which fits the constraint with a bit of extra
space.
Fixes:
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.. | ||
Kconfig | ||
ksz8795.c | ||
ksz8795_reg.h | ||
ksz8795_spi.c | ||
ksz9477.c | ||
ksz9477_i2c.c | ||
ksz9477_reg.h | ||
ksz9477_spi.c | ||
ksz_common.c | ||
ksz_common.h | ||
Makefile |