0d54d8f7a1
Currently the driver only supports 802.1Q VLAN insertion and stripping. However, once Double VLAN Mode (DVM) is fully supported, then both 802.1Q and 802.1ad VLAN insertion and stripping will be supported. Unfortunately the VSI context parameters only allow for one VLAN ethertype at a time for VLAN offloads so only one or the other VLAN ethertype offload can be supported at once. To support this, multiple changes are needed. Rx path changes: [1] In DVM, the Rx queue context l2tagsel field needs to be cleared so the outermost tag shows up in the l2tag2_2nd field of the Rx flex descriptor. In Single VLAN Mode (SVM), the l2tagsel field should remain 1 to support SVM configurations. [2] Modify the ice_test_staterr() function to take a __le16 instead of the ice_32b_rx_flex_desc union pointer so this function can be used for both rx_desc->wb.status_error0 and rx_desc->wb.status_error1. [3] Add the new inline function ice_get_vlan_tag_from_rx_desc() that checks if there is a VLAN tag in l2tag1 or l2tag2_2nd. [4] In ice_receive_skb(), add a check to see if NETIF_F_HW_VLAN_STAG_RX is enabled in netdev->features. If it is, then this is the VLAN ethertype that needs to be added to the stripping VLAN tag. Since ice_fix_features() prevents CTAG_RX and STAG_RX from being enabled simultaneously, the VLAN ethertype will only ever be 802.1Q or 802.1ad. Tx path changes: [1] In DVM, the VLAN tag needs to be placed in the l2tag2 field of the Tx context descriptor. The new define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN was added to the list of tx_flags to handle this case. [2] When the stack requests the VLAN tag to be offloaded on Tx, the driver needs to set either ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN or ICE_TX_FLAGS_HW_VLAN, so the tag is inserted in l2tag2 or l2tag1 respectively. To determine which location to use, set a bit in the Tx ring flags field during ring allocation that can be used to determine which field to use in the Tx descriptor. In DVM, always use l2tag2, and in SVM, always use l2tag1. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Tested-by: Gurucharan G <gurucharanx.g@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/* Copyright (c) 2019, Intel Corporation. */
|
|
|
|
#ifndef _ICE_TXRX_LIB_H_
|
|
#define _ICE_TXRX_LIB_H_
|
|
#include "ice.h"
|
|
|
|
/**
|
|
* ice_test_staterr - tests bits in Rx descriptor status and error fields
|
|
* @status_err_n: Rx descriptor status_error0 or status_error1 bits
|
|
* @stat_err_bits: value to mask
|
|
*
|
|
* This function does some fast chicanery in order to return the
|
|
* value of the mask which is really only used for boolean tests.
|
|
* The status_error_len doesn't need to be shifted because it begins
|
|
* at offset zero.
|
|
*/
|
|
static inline bool
|
|
ice_test_staterr(__le16 status_err_n, const u16 stat_err_bits)
|
|
{
|
|
return !!(status_err_n & cpu_to_le16(stat_err_bits));
|
|
}
|
|
|
|
static inline __le64
|
|
ice_build_ctob(u64 td_cmd, u64 td_offset, unsigned int size, u64 td_tag)
|
|
{
|
|
return cpu_to_le64(ICE_TX_DESC_DTYPE_DATA |
|
|
(td_cmd << ICE_TXD_QW1_CMD_S) |
|
|
(td_offset << ICE_TXD_QW1_OFFSET_S) |
|
|
((u64)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
|
|
(td_tag << ICE_TXD_QW1_L2TAG1_S));
|
|
}
|
|
|
|
/**
|
|
* ice_get_vlan_tag_from_rx_desc - get VLAN from Rx flex descriptor
|
|
* @rx_desc: Rx 32b flex descriptor with RXDID=2
|
|
*
|
|
* The OS and current PF implementation only support stripping a single VLAN tag
|
|
* at a time, so there should only ever be 0 or 1 tags in the l2tag* fields. If
|
|
* one is found return the tag, else return 0 to mean no VLAN tag was found.
|
|
*/
|
|
static inline u16
|
|
ice_get_vlan_tag_from_rx_desc(union ice_32b_rx_flex_desc *rx_desc)
|
|
{
|
|
u16 stat_err_bits;
|
|
|
|
stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S);
|
|
if (ice_test_staterr(rx_desc->wb.status_error0, stat_err_bits))
|
|
return le16_to_cpu(rx_desc->wb.l2tag1);
|
|
|
|
stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
|
|
if (ice_test_staterr(rx_desc->wb.status_error1, stat_err_bits))
|
|
return le16_to_cpu(rx_desc->wb.l2tag2_2nd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ice_xdp_ring_update_tail - Updates the XDP Tx ring tail register
|
|
* @xdp_ring: XDP Tx ring
|
|
*
|
|
* This function updates the XDP Tx ring tail register.
|
|
*/
|
|
static inline void ice_xdp_ring_update_tail(struct ice_tx_ring *xdp_ring)
|
|
{
|
|
/* Force memory writes to complete before letting h/w
|
|
* know there are new descriptors to fetch.
|
|
*/
|
|
wmb();
|
|
writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
|
|
}
|
|
|
|
void ice_finalize_xdp_rx(struct ice_tx_ring *xdp_ring, unsigned int xdp_res);
|
|
int ice_xmit_xdp_buff(struct xdp_buff *xdp, struct ice_tx_ring *xdp_ring);
|
|
int ice_xmit_xdp_ring(void *data, u16 size, struct ice_tx_ring *xdp_ring);
|
|
void ice_release_rx_desc(struct ice_rx_ring *rx_ring, u16 val);
|
|
void
|
|
ice_process_skb_fields(struct ice_rx_ring *rx_ring,
|
|
union ice_32b_rx_flex_desc *rx_desc,
|
|
struct sk_buff *skb, u16 ptype);
|
|
void
|
|
ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tag);
|
|
#endif /* !_ICE_TXRX_LIB_H_ */
|