fd534e9b5f
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 50 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190523091649.499889647@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
197 lines
4.8 KiB
C
197 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
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*/
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#ifndef __AR7_H__
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#define __AR7_H__
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/addrspace.h>
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#define AR7_SDRAM_BASE 0x14000000
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#define AR7_REGS_BASE 0x08610000
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#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
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#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
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/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
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#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
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#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
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#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
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#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
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#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
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#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
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#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
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#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
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#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
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#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
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#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
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#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
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#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
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#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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/* Titan registers */
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#define TITAN_REGS_ESWITCH_BASE (0x08640000)
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#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
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#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
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#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
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#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
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#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
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#define AR7_RESET_PERIPHERAL 0x0
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_STATUS 0x8
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#define AR7_RESET_BIT_CPMAC_LO 17
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#define AR7_RESET_BIT_CPMAC_HI 21
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#define AR7_RESET_BIT_MDIO 22
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#define AR7_RESET_BIT_EPHY 26
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#define TITAN_RESET_BIT_EPHY1 28
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/* GPIO control registers */
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#define AR7_GPIO_INPUT 0x0
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#define AR7_GPIO_OUTPUT 0x4
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#define AR7_GPIO_DIR 0x8
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#define AR7_GPIO_ENABLE 0xc
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#define TITAN_GPIO_INPUT_0 0x0
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#define TITAN_GPIO_INPUT_1 0x4
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#define TITAN_GPIO_OUTPUT_0 0x8
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#define TITAN_GPIO_OUTPUT_1 0xc
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#define TITAN_GPIO_DIR_0 0x10
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#define TITAN_GPIO_DIR_1 0x14
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#define TITAN_GPIO_ENBL_0 0x18
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#define TITAN_GPIO_ENBL_1 0x1c
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#define AR7_CHIP_7100 0x18
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#define AR7_CHIP_7200 0x2b
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#define AR7_CHIP_7300 0x05
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#define AR7_CHIP_TITAN 0x07
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#define TITAN_CHIP_1050 0x0f
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#define TITAN_CHIP_1055 0x0e
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#define TITAN_CHIP_1056 0x0d
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#define TITAN_CHIP_1060 0x07
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/* Interrupts */
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#define AR7_IRQ_UART0 15
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#define AR7_IRQ_UART1 16
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/* Clocks */
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#define AR7_AFE_CLOCK 35328000
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#define AR7_REF_CLOCK 25000000
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#define AR7_XTAL_CLOCK 24000000
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/* DCL */
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#define AR7_WDT_HW_ENA 0x10
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struct plat_cpmac_data {
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int reset_bit;
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int power_bit;
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u32 phy_mask;
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char dev_addr[6];
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};
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struct plat_dsl_data {
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int reset_bit_dsl;
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int reset_bit_sar;
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};
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extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
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static inline int ar7_is_titan(void)
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{
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return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
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AR7_CHIP_TITAN;
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}
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static inline u16 ar7_chip_id(void)
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{
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return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
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KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
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}
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static inline u16 titan_chip_id(void)
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{
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unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
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TITAN_GPIO_INPUT_1));
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return ((val >> 12) & 0x0f);
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}
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static inline u8 ar7_chip_rev(void)
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{
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return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
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0x14))) >> 16) & 0xff;
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}
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struct clk {
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unsigned int rate;
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};
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static inline int ar7_has_high_cpmac(void)
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{
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u16 chip_id = ar7_chip_id();
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switch (chip_id) {
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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return 0;
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case AR7_CHIP_7300:
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return 1;
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default:
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return -ENXIO;
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}
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}
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#define ar7_has_high_vlynq ar7_has_high_cpmac
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#define ar7_has_second_uart ar7_has_high_cpmac
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static inline void ar7_device_enable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
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writel(readl(reset_reg) | (1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_disable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
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writel(readl(reset_reg) & ~(1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_reset(u32 bit)
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{
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ar7_device_disable(bit);
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ar7_device_enable(bit);
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}
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static inline void ar7_device_on(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) | (1 << bit), power_reg);
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msleep(20);
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}
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static inline void ar7_device_off(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) & ~(1 << bit), power_reg);
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msleep(20);
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}
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int __init ar7_gpio_init(void);
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void __init ar7_init_clocks(void);
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/* Board specific GPIO functions */
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int ar7_gpio_enable(unsigned gpio);
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int ar7_gpio_disable(unsigned gpio);
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#endif /* __AR7_H__ */
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