2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* CPU feature overrides for DECstation systems. Two variations
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* are generally applicable.
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*
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* Copyright (C) 2013 Maciej W. Rozycki
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*/
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#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
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/* Generic ones first. */
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#define cpu_has_tlb 1
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#define cpu_has_tlbinv 0
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#define cpu_has_segments 0
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#define cpu_has_eva 0
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#define cpu_has_htw 0
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#define cpu_has_rixiex 0
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#define cpu_has_maar 0
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#define cpu_has_rw_llb 0
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#define cpu_has_tx39_cache 0
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#define cpu_has_divec 0
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#define cpu_has_prefetch 0
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#define cpu_has_mcheck 0
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#define cpu_has_ejtag 0
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_rixi 0
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#define cpu_has_xpa 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_pindexed_dcache 0
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#define cpu_has_local_ebase 0
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#define cpu_icache_snoops_remote_store 1
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#define cpu_has_mips_4 0
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#define cpu_has_mips_5 0
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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#define cpu_hwrena_impl_bits 0
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#define cpu_has_perf_cntr_intr_bit 0
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#define cpu_has_vz 0
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#define cpu_has_fre 0
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#define cpu_has_cdmm 0
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/* R3k-specific ones. */
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#ifdef CONFIG_CPU_R3000
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#define cpu_has_3kex 1
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#define cpu_has_4kex 0
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#define cpu_has_3k_cache 1
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#define cpu_has_4k_cache 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 0
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#define cpu_has_watch 0
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_llsc 0
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#define cpu_has_dc_aliases 0
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#define cpu_has_mips_2 0
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#define cpu_has_mips_3 0
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#define cpu_has_nofpuex 1
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#define cpu_has_inclusive_pcaches 0
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#define cpu_dcache_line_size() 4
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#define cpu_icache_line_size() 4
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#define cpu_scache_line_size() 0
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#endif /* CONFIG_CPU_R3000 */
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/* R4k-specific ones. */
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#ifdef CONFIG_CPU_R4X00
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#define cpu_has_3kex 0
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_32fpr 1
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_vce 1
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#define cpu_has_cache_cdex_p 1
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#define cpu_has_cache_cdex_s 1
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#define cpu_has_llsc 1
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#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
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#define cpu_has_mips_2 1
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#define cpu_has_mips_3 1
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#define cpu_has_nofpuex 0
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#define cpu_has_inclusive_pcaches 1
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#define cpu_dcache_line_size() 16
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#define cpu_icache_line_size() 16
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#define cpu_scache_line_size() 32
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#endif /* CONFIG_CPU_R4X00 */
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#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */
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