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linux/drivers/gpu
Umesh Nerlige Ramappa 2a67b18e67 drm/i915/pmu: Fix synchronization of PMU callback with reset
Since the PMU callback runs in irq context, it synchronizes with gt
reset using the reset count. We could run into a case where the PMU
callback could read the reset count before it is updated. This has a
potential of corrupting the busyness stats.

In addition to the reset count, check if the reset bit is set before
capturing busyness.

In addition save the previous stats only if you intend to update them.

v2:
- The 2 reset counts captured in the PMU callback can end up being the
  same if they were captured right after the count is incremented in the
  reset flow. This can lead to a bad busyness state. Ensure that reset
  is not in progress when the initial reset count is captured.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211108211057.68783-1-umesh.nerlige.ramappa@intel.com
2021-11-30 17:08:07 -08:00
..
drm drm/i915/pmu: Fix synchronization of PMU callback with reset 2021-11-30 17:08:07 -08:00
host1x gpu: host1x: Plug potential memory leak 2021-09-16 18:06:52 +02:00
ipu-v3 media: i.MX6: Support 16-bit BT.1120 video input 2021-10-19 08:08:38 +01:00
trace
vga vgaarb: don't pass a cookie to vga_client_register 2021-07-21 10:29:10 +02:00
Makefile