1e3dc1d862
GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-2-daniele.ceraolospurio@intel.com
130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_GT__
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#define __INTEL_GT__
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#include "intel_engine_types.h"
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#include "intel_gt_types.h"
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#include "intel_reset.h"
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struct drm_i915_private;
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struct drm_printer;
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struct insert_entries {
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struct i915_address_space *vm;
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struct i915_vma_resource *vma_res;
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enum i915_cache_level level;
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u32 flags;
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};
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#define GT_TRACE(gt, fmt, ...) do { \
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const struct intel_gt *gt__ __maybe_unused = (gt); \
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GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
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##__VA_ARGS__); \
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} while (0)
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static inline bool gt_is_root(struct intel_gt *gt)
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{
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return !gt->info.id;
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}
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static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
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{
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return container_of(uc, struct intel_gt, uc);
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}
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static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
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{
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return container_of(guc, struct intel_gt, uc.guc);
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}
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static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
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{
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return container_of(huc, struct intel_gt, uc.huc);
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}
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static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
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{
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return container_of(gsc, struct intel_gt, gsc);
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}
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void intel_root_gt_init_early(struct drm_i915_private *i915);
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int intel_gt_assign_ggtt(struct intel_gt *gt);
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int intel_gt_init_mmio(struct intel_gt *gt);
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int __must_check intel_gt_init_hw(struct intel_gt *gt);
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int intel_gt_init(struct intel_gt *gt);
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void intel_gt_driver_register(struct intel_gt *gt);
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void intel_gt_driver_unregister(struct intel_gt *gt);
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void intel_gt_driver_remove(struct intel_gt *gt);
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void intel_gt_driver_release(struct intel_gt *gt);
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void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
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int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
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void intel_gt_check_and_clear_faults(struct intel_gt *gt);
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void intel_gt_clear_error_registers(struct intel_gt *gt,
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intel_engine_mask_t engine_mask);
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void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
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void intel_gt_chipset_flush(struct intel_gt *gt);
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static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
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enum intel_gt_scratch_field field)
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{
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return i915_ggtt_offset(gt->scratch) + field;
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}
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static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
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{
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return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) ||
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test_bit(I915_WEDGED_ON_FINI, >->reset.flags);
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}
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static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
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{
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GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
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!test_bit(I915_WEDGED, >->reset.flags));
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return unlikely(test_bit(I915_WEDGED, >->reset.flags));
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}
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static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
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enum intel_steering_type type)
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{
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return gt->steering_table[type];
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}
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void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg,
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u8 *sliceid, u8 *subsliceid);
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u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
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u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
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void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
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bool dump_table);
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int intel_gt_probe_all(struct drm_i915_private *i915);
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int intel_gt_tiles_init(struct drm_i915_private *i915);
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void intel_gt_release_all(struct drm_i915_private *i915);
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#define for_each_gt(gt__, i915__, id__) \
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for ((id__) = 0; \
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(id__) < I915_MAX_GT; \
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(id__)++) \
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for_each_if(((gt__) = (i915__)->gt[(id__)]))
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void intel_gt_info_print(const struct intel_gt_info *info,
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struct drm_printer *p);
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void intel_gt_watchdog_work(struct work_struct *work);
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void intel_gt_invalidate_tlbs(struct intel_gt *gt);
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struct resource intel_pci_resource(struct pci_dev *pdev, int bar);
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#endif /* __INTEL_GT_H__ */
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