7af5b901e8
With LPAE enabled, privileged no-access cannot be enforced using CPU domains as such feature is not available. This patch implements PAN by disabling TTBR0 page table walks while in kernel mode. The ARM architecture allows page table walks to be split between TTBR0 and TTBR1. With LPAE enabled, the split is defined by a combination of TTBCR T0SZ and T1SZ bits. Currently, an LPAE-enabled kernel uses TTBR0 for user addresses and TTBR1 for kernel addresses with the VMSPLIT_2G and VMSPLIT_3G configurations. The main advantage for the 3:1 split is that TTBR1 is reduced to 2 levels, so potentially faster TLB refill (though usually the first level entries are already cached in the TLB). The PAN support on LPAE-enabled kernels uses TTBR0 when running in user space or in kernel space during user access routines (TTBCR T0SZ and T1SZ are both 0). When running user accesses are disabled in kernel mode, TTBR0 page table walks are disabled by setting TTBCR.EPD0. TTBR1 is used for kernel accesses (including loadable modules; anything covered by swapper_pg_dir) by reducing the TTBCR.T0SZ to the minimum (2^(32-7) = 32MB). To avoid user accesses potentially hitting stale TLB entries, the ASID is switched to 0 (reserved) by setting TTBCR.A1 and using the ASID value in TTBR1. The difference from a non-PAN kernel is that with the 3:1 memory split, TTBR1 always uses 3 levels of page tables. As part of the change we are using preprocessor elif definied() clauses so balance these clauses by converting relevant precedingt ifdef clauses to if defined() clauses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
202 lines
4.9 KiB
C
202 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/ptrace.h
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*
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* Copyright (C) 1996-2003 Russell King
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*/
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#ifndef __ASM_ARM_PTRACE_H
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#define __ASM_ARM_PTRACE_H
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#include <uapi/asm/ptrace.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitfield.h>
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#include <linux/types.h>
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struct pt_regs {
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unsigned long uregs[18];
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};
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struct svc_pt_regs {
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struct pt_regs regs;
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u32 dacr;
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u32 ttbcr;
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};
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#define to_svc_pt_regs(r) container_of(r, struct svc_pt_regs, regs)
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#define user_mode(regs) \
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(((regs)->ARM_cpsr & 0xf) == 0)
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#ifdef CONFIG_ARM_THUMB
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#define thumb_mode(regs) \
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(((regs)->ARM_cpsr & PSR_T_BIT))
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#else
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#define thumb_mode(regs) (0)
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#endif
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#ifndef CONFIG_CPU_V7M
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#define isa_mode(regs) \
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(FIELD_GET(PSR_J_BIT, (regs)->ARM_cpsr) << 1 | \
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FIELD_GET(PSR_T_BIT, (regs)->ARM_cpsr))
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#else
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#define isa_mode(regs) 1 /* Thumb */
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#endif
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#define processor_mode(regs) \
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((regs)->ARM_cpsr & MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_F_BIT))
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/* Are the current registers suitable for user mode?
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* (used to maintain security in signal handlers)
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*/
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static inline int valid_user_regs(struct pt_regs *regs)
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{
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#ifndef CONFIG_CPU_V7M
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unsigned long mode = regs->ARM_cpsr & MODE_MASK;
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/*
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* Always clear the F (FIQ) and A (delayed abort) bits
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*/
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regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
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if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
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if (mode == USR_MODE)
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return 1;
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if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
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return 1;
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}
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/*
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* Force CPSR to something logical...
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*/
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regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
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if (!(elf_hwcap & HWCAP_26BIT))
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regs->ARM_cpsr |= USR_MODE;
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return 0;
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#else /* ifndef CONFIG_CPU_V7M */
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return 1;
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#endif
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}
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static inline long regs_return_value(struct pt_regs *regs)
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{
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return regs->ARM_r0;
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}
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#define instruction_pointer(regs) (regs)->ARM_pc
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#ifdef CONFIG_THUMB2_KERNEL
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#define frame_pointer(regs) (regs)->ARM_r7
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#else
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#define frame_pointer(regs) (regs)->ARM_fp
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#endif
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static inline void instruction_pointer_set(struct pt_regs *regs,
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unsigned long val)
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{
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instruction_pointer(regs) = val;
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}
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#ifdef CONFIG_SMP
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extern unsigned long profile_pc(struct pt_regs *regs);
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#else
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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#define predicate(x) ((x) & 0xf0000000)
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#define PREDICATE_ALWAYS 0xe0000000
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/*
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* True if instr is a 32-bit thumb instruction. This works if instr
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* is the first or only half-word of a thumb instruction. It also works
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* when instr holds all 32-bits of a wide thumb instruction if stored
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* in the form (first_half<<16)|(second_half)
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*/
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#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
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/*
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* kprobe-based event tracer support
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*/
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#include <linux/compiler.h>
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#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
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extern int regs_query_register_offset(const char *name);
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extern const char *regs_query_register_name(unsigned int offset);
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extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
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extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
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unsigned int n);
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/**
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* regs_get_register() - get register value from its offset
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* @regs: pt_regs from which register value is gotten
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* @offset: offset number of the register.
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*
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* regs_get_register returns the value of a register whose offset from @regs.
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* The @offset is the offset of the register in struct pt_regs.
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
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*/
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static inline unsigned long regs_get_register(struct pt_regs *regs,
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unsigned int offset)
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{
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if (unlikely(offset > MAX_REG_OFFSET))
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return 0;
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return *(unsigned long *)((unsigned long)regs + offset);
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}
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/* Valid only for Kernel mode traps. */
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static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
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{
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return regs->ARM_sp;
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}
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static inline unsigned long user_stack_pointer(struct pt_regs *regs)
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{
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return regs->ARM_sp;
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}
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#define current_pt_regs(void) ({ (struct pt_regs *) \
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((current_stack_pointer | (THREAD_SIZE - 1)) - 7) - 1; \
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})
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static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
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{
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regs->ARM_r0 = rc;
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}
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/*
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* Update ITSTATE after normal execution of an IT block instruction.
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*
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* The 8 IT state bits are split into two parts in CPSR:
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* ITSTATE<1:0> are in CPSR<26:25>
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* ITSTATE<7:2> are in CPSR<15:10>
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*/
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static inline unsigned long it_advance(unsigned long cpsr)
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{
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if ((cpsr & 0x06000400) == 0) {
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/* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
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cpsr &= ~PSR_IT_MASK;
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} else {
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/* We need to shift left ITSTATE<4:0> */
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const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */
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unsigned long it = cpsr & mask;
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it <<= 1;
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it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */
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it &= mask;
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cpsr &= ~mask;
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cpsr |= it;
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}
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return cpsr;
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}
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int syscall_trace_enter(struct pt_regs *regs);
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void syscall_trace_exit(struct pt_regs *regs);
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#endif /* __ASSEMBLY__ */
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#endif
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