5e9d13bd3d
Now the exception vector for CPS systems are allocated on-fly
with memblock as well.
It will try to allocate from KSEG1 first, and then try to allocate
in low 4G if possible.
The main reset vector is now generated by uasm, to avoid tons
of patches to the code. Other vectors are copied to the location
later.
move 64bits fix in an other patch
fix cache issue with mips_cps_core_entry
rewrite the patch to reduce the diff stat
move extern in header
use cache address for copying vector
gc: use the new macro CKSEG[0A1]DDR_OR_64BIT()
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
57 lines
1.2 KiB
C
57 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#ifndef __MIPS_ASM_SMP_CPS_H__
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#define __MIPS_ASM_SMP_CPS_H__
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#define CPS_ENTRY_PATCH_INSNS 6
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#ifndef __ASSEMBLY__
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struct vpe_boot_config {
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unsigned long pc;
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unsigned long sp;
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unsigned long gp;
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};
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struct core_boot_config {
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atomic_t vpe_mask;
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struct vpe_boot_config *vpe_config;
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};
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extern struct core_boot_config *mips_cps_core_bootcfg;
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extern void mips_cps_core_boot(int cca, void __iomem *gcr_base);
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extern void mips_cps_core_init(void);
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extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
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extern void mips_cps_pm_save(void);
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extern void mips_cps_pm_restore(void);
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extern void excep_tlbfill(void);
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extern void excep_xtlbfill(void);
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extern void excep_cache(void);
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extern void excep_genex(void);
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extern void excep_intex(void);
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extern void excep_ejtag(void);
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#ifdef CONFIG_MIPS_CPS
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extern bool mips_cps_smp_in_use(void);
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#else /* !CONFIG_MIPS_CPS */
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static inline bool mips_cps_smp_in_use(void) { return false; }
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#endif /* !CONFIG_MIPS_CPS */
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#else /* __ASSEMBLY__ */
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.extern mips_cps_bootcfg;
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#endif /* __ASSEMBLY__ */
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#endif /* __MIPS_ASM_SMP_CPS_H__ */
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