4dc70e1aad
My original, naive, FPU support patch had the FPCSR register stored during both the *mode switch* and *context switch*. This is wasteful. Also, the original patches did not save the FPU state when handling signals during the system call fast path. We fix this by moving the FPCSR state to thread_struct in task_struct. We also introduce new helper functions save_fpu and restore_fpu which can be used to sync the FPU with thread_struct. These functions are now called when needed: - Setting up and restoring sigcontext when handling signals - Before and after __switch_to during context switches - When handling FPU exceptions - When reading and writing FPU register sets In the future we can further optimize this by doing lazy FPU save and restore. For example, FPU sync is not needed when switching to and from kernel threads (x86 does this). FPU save and restore does not need to be done two times if we have both rescheduling and signal work to do. However, since OpenRISC FPU state is a single register, I leave these optimizations for future consideration. Signed-off-by: Stafford Horne <shorne@gmail.com>
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*/
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#ifndef __ASM_OPENRISC_PTRACE_H
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#define __ASM_OPENRISC_PTRACE_H
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#include <asm/spr_defs.h>
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#include <uapi/asm/ptrace.h>
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/*
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* Make kernel PTrace/register structures opaque to userspace... userspace can
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* access thread state via the regset mechanism. This allows us a bit of
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* flexibility in how we order the registers on the stack, permitting some
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* optimizations like packing call-clobbered registers together so that
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* they share a cacheline (not done yet, though... future optimization).
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*/
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#ifndef __ASSEMBLY__
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/*
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* This struct describes how the registers are laid out on the kernel stack
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* during a syscall or other kernel entry.
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*
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* This structure should always be cacheline aligned on the stack.
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* FIXME: I don't think that's the case right now. The alignment is
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* taken care of elsewhere... head.S, process.c, etc.
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*/
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struct pt_regs {
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union {
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struct {
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/* Named registers */
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long sr; /* Stored in place of r0 */
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long sp; /* r1 */
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};
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struct {
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/* Old style */
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long offset[2];
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long gprs[30];
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};
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struct {
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/* New style */
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long gpr[32];
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};
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};
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long pc;
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/* For restarting system calls:
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* Set to syscall number for syscall exceptions,
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* -1 for all other exceptions.
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*/
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long orig_gpr11; /* For restarting system calls */
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long dummy; /* Cheap alignment fix */
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long dummy2; /* Cheap alignment fix */
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};
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/* TODO: Rename this to REDZONE because that's what it is */
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#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
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#define instruction_pointer(regs) ((regs)->pc)
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#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0)
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#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
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#define profile_pc(regs) instruction_pointer(regs)
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static inline long regs_return_value(struct pt_regs *regs)
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{
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return regs->gpr[11];
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}
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#endif /* __ASSEMBLY__ */
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/*
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* Offsets used by 'ptrace' system call interface.
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*/
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#define PT_SR 0
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#define PT_SP 4
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#define PT_GPR2 8
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#define PT_GPR3 12
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#define PT_GPR4 16
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#define PT_GPR5 20
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#define PT_GPR6 24
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#define PT_GPR7 28
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#define PT_GPR8 32
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#define PT_GPR9 36
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#define PT_GPR10 40
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#define PT_GPR11 44
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#define PT_GPR12 48
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#define PT_GPR13 52
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#define PT_GPR14 56
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#define PT_GPR15 60
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#define PT_GPR16 64
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#define PT_GPR17 68
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#define PT_GPR18 72
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#define PT_GPR19 76
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#define PT_GPR20 80
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#define PT_GPR21 84
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#define PT_GPR22 88
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#define PT_GPR23 92
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#define PT_GPR24 96
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#define PT_GPR25 100
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#define PT_GPR26 104
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#define PT_GPR27 108
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#define PT_GPR28 112
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#define PT_GPR29 116
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#define PT_GPR30 120
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#define PT_GPR31 124
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#define PT_PC 128
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#define PT_ORIG_GPR11 132
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#endif /* __ASM_OPENRISC_PTRACE_H */
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