9c7bfc2dc2
We want to move away from using SMT priority updates for cpu_relax, and use a 'wait' instruction which is similar to x86. As well as being a much better fit for what everybody else uses and tests with, priority nops are stateful which is nasty (interrupts have to consider they might be taken at a different priority), and they're expensive to execute, similar to a mtSPR which can effect other threads in the pipe. This has shown to give results that are less affected by code alignment on benchmarks that cause a lot of spin waiting (e.g., rwsem contention on unixbench filesystem benchmarks) on POWER10. QEMU TCG only supports this instruction correctly since v7.1, versions without the fix may cause hangs whne running POWER10 CPUs. Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Fix checkpatch warnings RE the macros] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220920122259.363092-2-npiggin@gmail.com
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_POWERPC_VDSO_PROCESSOR_H
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#define _ASM_POWERPC_VDSO_PROCESSOR_H
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#ifndef __ASSEMBLY__
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/* Macros for adjusting thread priority (hardware multi-threading) */
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#ifdef CONFIG_PPC64
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#define HMT_very_low() asm volatile("or 31, 31, 31 # very low priority")
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#define HMT_low() asm volatile("or 1, 1, 1 # low priority")
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#define HMT_medium_low() asm volatile("or 6, 6, 6 # medium low priority")
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#define HMT_medium() asm volatile("or 2, 2, 2 # medium priority")
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#define HMT_medium_high() asm volatile("or 5, 5, 5 # medium high priority")
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#define HMT_high() asm volatile("or 3, 3, 3 # high priority")
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#else
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#define HMT_very_low()
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#define HMT_low()
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#define HMT_medium_low()
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#define HMT_medium()
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#define HMT_medium_high()
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#define HMT_high()
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#endif
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#ifdef CONFIG_PPC64
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#define cpu_relax() \
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asm volatile(ASM_FTR_IFCLR( \
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/* Pre-POWER10 uses low ; medium priority nops */ \
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"or 1,1,1 ; or 2,2,2", \
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/* POWER10 onward uses pause_short (wait 2,0) */ \
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PPC_WAIT(2, 0), \
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%0) :: "i" (CPU_FTR_ARCH_31) : "memory")
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#else
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#define cpu_relax() barrier()
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_VDSO_PROCESSOR_H */
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