a23eb2fc1d
The current perf assumes that the counters that support PEBS are contiguous. But it's not guaranteed with the new leaf 0x23 introduced. The counters are enumerated with a counter mask. There may be holes in the counter mask for future platforms or in a virtualization environment. Store the PEBS event mask rather than the maximum number of PEBS counters in the x86 PMU structures. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Ian Rogers <irogers@google.com> Link: https://lkml.kernel.org/r/20240626143545.480761-2-kan.liang@linux.intel.com
39 lines
947 B
C
39 lines
947 B
C
#ifndef _ASM_INTEL_DS_H
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#define _ASM_INTEL_DS_H
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#include <linux/percpu-defs.h>
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#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
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#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
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/* The maximal number of PEBS events: */
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#define MAX_PEBS_EVENTS_FMT4 8
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#define MAX_PEBS_EVENTS 32
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#define MAX_PEBS_EVENTS_MASK GENMASK_ULL(MAX_PEBS_EVENTS - 1, 0)
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#define MAX_FIXED_PEBS_EVENTS 16
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
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} __aligned(PAGE_SIZE);
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DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
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struct debug_store_buffers {
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char bts_buffer[BTS_BUFFER_SIZE];
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char pebs_buffer[PEBS_BUFFER_SIZE];
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};
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#endif
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