0340906952
Modern CPUs all share the same MTRR interface implemented via generic_mtrr_ops. At several places in MTRR code this generic interface is deduced via is_cpu(INTEL) tests, which is only working due to X86_VENDOR_INTEL being 0 (the is_cpu() macro is testing mtrr_if->vendor, which isn't explicitly set in generic_mtrr_ops). Test the generic CPU feature X86_FEATURE_MTRR instead. The only other place where the .vendor member of struct mtrr_ops is being used is in set_num_var_ranges(), where depending on the vendor the number of MTRR registers is determined. This can easily be changed by replacing .vendor with the static number of MTRR registers. It should be noted that the test "is_cpu(HYGON)" wasn't ever returning true, as there is no struct mtrr_ops with that vendor information. [ bp: Use mtrr_enabled() before doing mtrr_if-> accesses, esp. in mtrr_trim_uncached_memory() which gets called independently from whether mtrr_if is set or not. ] Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230502120931.20719-7-jgross@suse.com Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
119 lines
3 KiB
C
119 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "mtrr.h"
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static void
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amd_get_mtrr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type *type)
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{
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unsigned long low, high;
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rdmsr(MSR_K6_UWCCR, low, high);
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/* Upper dword is region 1, lower is region 0 */
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if (reg == 1)
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low = high;
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/* The base masks off on the right alignment */
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*base = (low & 0xFFFE0000) >> PAGE_SHIFT;
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*type = 0;
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if (low & 1)
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*type = MTRR_TYPE_UNCACHABLE;
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if (low & 2)
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*type = MTRR_TYPE_WRCOMB;
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if (!(low & 3)) {
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*size = 0;
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return;
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}
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/*
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* This needs a little explaining. The size is stored as an
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* inverted mask of bits of 128K granularity 15 bits long offset
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* 2 bits.
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*
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* So to get a size we do invert the mask and add 1 to the lowest
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* mask bit (4 as its 2 bits in). This gives us a size we then shift
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* to turn into 128K blocks.
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*
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* eg 111 1111 1111 1100 is 512K
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*
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* invert 000 0000 0000 0011
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* +1 000 0000 0000 0100
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* *128K ...
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*/
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low = (~low) & 0x1FFFC;
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*size = (low + 4) << (15 - PAGE_SHIFT);
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}
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/**
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* amd_set_mtrr - Set variable MTRR register on the local CPU.
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*
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* @reg The register to set.
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* @base The base address of the region.
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* @size The size of the region. If this is 0 the region is disabled.
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* @type The type of the region.
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*
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* Returns nothing.
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*/
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static void
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amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
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{
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u32 regs[2];
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/*
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* Low is MTRR0, High MTRR 1
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*/
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rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
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/*
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* Blank to disable
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*/
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if (size == 0) {
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regs[reg] = 0;
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} else {
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/*
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* Set the register to the base, the type (off by one) and an
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* inverted bitmask of the size The size is the only odd
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* bit. We are fed say 512K We invert this and we get 111 1111
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* 1111 1011 but if you subtract one and invert you get the
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* desired 111 1111 1111 1100 mask
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*
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* But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
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*/
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regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
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| (base << PAGE_SHIFT) | (type + 1);
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}
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/*
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* The writeback rule is quite specific. See the manual. Its
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* disable local interrupts, write back the cache, set the mtrr
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*/
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wbinvd();
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wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
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}
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static int
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amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
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{
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/*
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* Apply the K6 block alignment and size rules
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* In order
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* o Uncached or gathering only
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* o 128K or bigger block
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* o Power of 2 block
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* o base suitably aligned to the power
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*/
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if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
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|| (size & ~(size - 1)) - size || (base & (size - 1)))
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return -EINVAL;
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return 0;
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}
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const struct mtrr_ops amd_mtrr_ops = {
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.var_regs = 2,
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.set = amd_set_mtrr,
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.get = amd_get_mtrr,
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.get_free_region = generic_get_free_region,
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.validate_add_page = amd_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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