d80e44a34e
Add smuio callback to get gpu clk counter Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
62 lines
2.4 KiB
C
62 lines
2.4 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "smuio_v14_0_2.h"
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#include "smuio/smuio_14_0_2_offset.h"
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#include "smuio/smuio_14_0_2_sh_mask.h"
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#include <linux/preempt.h>
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static u32 smuio_v14_0_2_get_rom_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
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}
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static u32 smuio_v14_0_2_get_rom_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
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}
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static u64 smuio_v14_0_2_get_gpu_clock_counter(struct amdgpu_device *adev)
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{
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u64 clock;
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u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
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preempt_disable();
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clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
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clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
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/* the clock counter may be udpated during polling the counters */
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clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
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if (clock_counter_hi_pre != clock_counter_hi_after)
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clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
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preempt_enable();
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clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
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return clock;
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}
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const struct amdgpu_smuio_funcs smuio_v14_0_2_funcs = {
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.get_rom_index_offset = smuio_v14_0_2_get_rom_index_offset,
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.get_rom_data_offset = smuio_v14_0_2_get_rom_data_offset,
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.get_gpu_clock_counter = smuio_v14_0_2_get_gpu_clock_counter,
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};
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