6aff4c26ed
Due to a change in the order of initialization, the lid timer got
started before proper setup was made. This resulted in a crash during
boot.
The lid switch is handled by gma500 through a timer that periodically
polls the opregion for changes. These types of ACPI events shouldn't be
handled by the graphics driver so let's get rid of the lid code. This
fixes the crash during boot.
Reported-by: Enrico Bartky <enrico.bartky@gmail.com>
Fixes: 8f1aaccb04 ("drm/gma500: Implement client-based fbdev emulation")
Tested-by: Enrico Bartky <enrico.bartky@gmail.com>
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20240415112731.31841-1-patrik.r.jakobsson@gmail.com
293 lines
7.4 KiB
C
293 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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**************************************************************************/
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#include <drm/drm.h>
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#include <drm/drm_crtc_helper.h>
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#include "gma_device.h"
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#include "intel_bios.h"
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#include "psb_device.h"
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#include "psb_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_reg.h"
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static int psb_output_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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psb_intel_lvds_init(dev, &dev_priv->mode_dev);
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psb_intel_sdvo_init(dev, SDVOB);
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return 0;
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}
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/*
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* Poulsbo Backlight Interfaces
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*/
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define PSB_BLC_PWM_PRECISION_FACTOR 10
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#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
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#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
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#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
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#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
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static int psb_backlight_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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unsigned long core_clock;
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/* u32 bl_max_freq; */
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/* unsigned long value; */
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u16 bl_max_freq;
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uint32_t value;
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uint32_t blc_pwm_precision_factor;
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/* get bl_max_freq and pol from dev_priv*/
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if (!dev_priv->lvds_bl) {
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dev_err(dev->dev, "Has no valid LVDS backlight info\n");
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return -ENOENT;
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}
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bl_max_freq = dev_priv->lvds_bl->freq;
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blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
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core_clock = dev_priv->core_freq;
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value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
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value *= blc_pwm_precision_factor;
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value /= bl_max_freq;
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value /= blc_pwm_precision_factor;
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if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
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value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
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return -ERANGE;
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else {
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value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
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REG_WRITE(BLC_PWM_CTL,
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(value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
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}
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psb_intel_lvds_set_brightness(dev, PSB_MAX_BRIGHTNESS);
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return 0;
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}
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/*
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* Provide the Poulsbo specific chip logic and low level methods
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* for power management
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*/
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static void psb_init_pm(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
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gating &= ~3; /* Disable 2D clock gating */
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gating |= 1;
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PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
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PSB_RSGX32(PSB_CR_CLKGATECTL);
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}
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/**
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* psb_save_display_registers - save registers lost on suspend
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* @dev: our DRM device
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*
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* Save the state we need in order to be able to restore the interface
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* upon resume from suspend
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*/
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static int psb_save_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct gma_connector *gma_connector;
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struct drm_crtc *crtc;
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struct drm_connector_list_iter conn_iter;
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struct drm_connector *connector;
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struct psb_state *regs = &dev_priv->regs.psb;
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/* Display arbitration control + watermarks */
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regs->saveDSPARB = PSB_RVDC32(DSPARB);
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regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
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regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
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regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
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regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
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regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
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regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
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regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
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/* Save crtc and output state */
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drm_modeset_lock_all(dev);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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if (drm_helper_crtc_in_use(crtc))
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dev_priv->ops->save_crtc(crtc);
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}
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drm_connector_list_iter_begin(dev, &conn_iter);
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drm_for_each_connector_iter(connector, &conn_iter) {
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gma_connector = to_gma_connector(connector);
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if (gma_connector->save)
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gma_connector->save(connector);
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}
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drm_connector_list_iter_end(&conn_iter);
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drm_modeset_unlock_all(dev);
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return 0;
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}
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/**
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* psb_restore_display_registers - restore lost register state
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* @dev: our DRM device
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*
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* Restore register state that was lost during suspend and resume.
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*/
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static int psb_restore_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct gma_connector *gma_connector;
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struct drm_crtc *crtc;
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struct drm_connector_list_iter conn_iter;
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struct drm_connector *connector;
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struct psb_state *regs = &dev_priv->regs.psb;
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/* Display arbitration + watermarks */
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PSB_WVDC32(regs->saveDSPARB, DSPARB);
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PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
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PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
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PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
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PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
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PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
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PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
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PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
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/*make sure VGA plane is off. it initializes to on after reset!*/
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PSB_WVDC32(0x80000000, VGACNTRL);
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drm_modeset_lock_all(dev);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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if (drm_helper_crtc_in_use(crtc))
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dev_priv->ops->restore_crtc(crtc);
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drm_connector_list_iter_begin(dev, &conn_iter);
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drm_for_each_connector_iter(connector, &conn_iter) {
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gma_connector = to_gma_connector(connector);
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if (gma_connector->restore)
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gma_connector->restore(connector);
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}
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drm_connector_list_iter_end(&conn_iter);
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drm_modeset_unlock_all(dev);
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return 0;
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}
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static int psb_power_down(struct drm_device *dev)
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{
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return 0;
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}
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static int psb_power_up(struct drm_device *dev)
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{
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return 0;
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}
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/* Poulsbo */
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static const struct psb_offset psb_regmap[2] = {
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{
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.fp0 = FPA0,
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.fp1 = FPA1,
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.cntr = DSPACNTR,
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.conf = PIPEACONF,
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.src = PIPEASRC,
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.dpll = DPLL_A,
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.htotal = HTOTAL_A,
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.hblank = HBLANK_A,
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.hsync = HSYNC_A,
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.vtotal = VTOTAL_A,
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.vblank = VBLANK_A,
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.vsync = VSYNC_A,
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.stride = DSPASTRIDE,
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.size = DSPASIZE,
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.pos = DSPAPOS,
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.base = DSPABASE,
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.surf = DSPASURF,
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.addr = DSPABASE,
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.status = PIPEASTAT,
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.linoff = DSPALINOFF,
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.tileoff = DSPATILEOFF,
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.palette = PALETTE_A,
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},
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{
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.fp0 = FPB0,
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.fp1 = FPB1,
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.cntr = DSPBCNTR,
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.conf = PIPEBCONF,
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.src = PIPEBSRC,
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.dpll = DPLL_B,
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.htotal = HTOTAL_B,
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.hblank = HBLANK_B,
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.hsync = HSYNC_B,
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.vtotal = VTOTAL_B,
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.vblank = VBLANK_B,
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.vsync = VSYNC_B,
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.stride = DSPBSTRIDE,
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.size = DSPBSIZE,
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.pos = DSPBPOS,
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.base = DSPBBASE,
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.surf = DSPBSURF,
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.addr = DSPBBASE,
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.status = PIPEBSTAT,
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.linoff = DSPBLINOFF,
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.tileoff = DSPBTILEOFF,
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.palette = PALETTE_B,
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}
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};
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static int psb_chip_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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dev_priv->regmap = psb_regmap;
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gma_get_core_freq(dev);
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gma_intel_setup_gmbus(dev);
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psb_intel_opregion_init(dev);
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psb_intel_init_bios(dev);
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return 0;
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}
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static void psb_chip_teardown(struct drm_device *dev)
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{
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gma_intel_teardown_gmbus(dev);
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}
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const struct psb_ops psb_chip_ops = {
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.name = "Poulsbo",
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.pipes = 2,
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.crtcs = 2,
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.hdmi_mask = (1 << 0),
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.lvds_mask = (1 << 1),
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.sdvo_mask = (1 << 0),
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.cursor_needs_phys = 1,
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.sgx_offset = PSB_SGX_OFFSET,
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.chip_setup = psb_chip_setup,
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.chip_teardown = psb_chip_teardown,
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.crtc_helper = &psb_intel_helper_funcs,
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.clock_funcs = &psb_clock_funcs,
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.output_init = psb_output_init,
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.backlight_init = psb_backlight_setup,
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.backlight_set = psb_intel_lvds_set_brightness,
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.backlight_name = "psb-bl",
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.init_pm = psb_init_pm,
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.save_regs = psb_save_display_registers,
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.restore_regs = psb_restore_display_registers,
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.save_crtc = gma_crtc_save,
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.restore_crtc = gma_crtc_restore,
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.power_down = psb_power_down,
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.power_up = psb_power_up,
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};
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