7b1f6b5aae
Currently we always reprogram CDCLK from the intel_set_cdclk_pre_plane_update() when using squash/crawl. The code only works correctly for the cd2x update or full modeset cases, and it was simply never updated to deal with squash/crawl. If the CDCLK frequency is increasing we must reprogram it before we do anything else that might depend on the new higher frequency, and conversely we must not decrease the frequency until everything that might still depend on the old higher frequency has been dealt with. Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use it to determine the correct sequence during squash/crawl. To that end introduce cdclk_state->disable_pipes which simply indicates that we must perform the update while the pipes are disable (ie. during intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new CDCLK frequency comparsiong as for cd2x updates. The only remaining problem case is when the voltage_level needs to increase due to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are being disabled). The current approach will not bump the voltage level up until after the port has already been enabled, which is too late. But we'll take care of that case separately. v2: Don't break the "must disable pipes case" v3: Keep the on stack 'pipe' for future use Cc: stable@vger.kernel.org Fixes:d62686ba3b("drm/i915/adl_p: CDCLK crawl support for ADL") Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-2-ville.syrjala@linux.intel.com (cherry picked from commit3aecee90ac) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_CDCLK_H__
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#define __INTEL_CDCLK_H__
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#include <linux/types.h>
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#include "intel_display_limits.h"
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#include "intel_global_state.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_cdclk_config {
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unsigned int cdclk, vco, ref, bypass;
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u8 voltage_level;
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/* This field is only valid for Xe2LPD and above. */
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bool joined_mbus;
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};
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struct intel_cdclk_state {
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struct intel_global_state base;
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/*
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* Logical configuration of cdclk (used for all scaling,
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* watermark, etc. calculations and checks). This is
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* computed as if all enabled crtcs were active.
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*/
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struct intel_cdclk_config logical;
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/*
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* Actual configuration of cdclk, can be different from the
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* logical configuration only when all crtc's are DPMS off.
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*/
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struct intel_cdclk_config actual;
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/* minimum acceptable cdclk to satisfy bandwidth requirements */
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int bw_min_cdclk;
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/* minimum acceptable cdclk for each pipe */
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int min_cdclk[I915_MAX_PIPES];
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/* minimum acceptable voltage level for each pipe */
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u8 min_voltage_level[I915_MAX_PIPES];
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/* pipe to which cd2x update is synchronized */
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enum pipe pipe;
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/* forced minimum cdclk for glk+ audio w/a */
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int force_min_cdclk;
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/* bitmask of active pipes */
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u8 active_pipes;
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/* update cdclk with pipes disabled */
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bool disable_pipes;
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};
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int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
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void intel_cdclk_init_hw(struct drm_i915_private *i915);
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void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
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void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
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void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
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void intel_update_cdclk(struct drm_i915_private *dev_priv);
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u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
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bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b);
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int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
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const struct intel_cdclk_config *cdclk_config);
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bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
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void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
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void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
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void intel_cdclk_dump_config(struct drm_i915_private *i915,
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const struct intel_cdclk_config *cdclk_config,
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const char *context);
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int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
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void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
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struct intel_cdclk_config *cdclk_config);
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int intel_cdclk_atomic_check(struct intel_atomic_state *state,
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bool *need_cdclk_calc);
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int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus);
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struct intel_cdclk_state *
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intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
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#define to_intel_cdclk_state(global_state) \
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container_of_const((global_state), struct intel_cdclk_state, base)
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#define intel_atomic_get_old_cdclk_state(state) \
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to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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#define intel_atomic_get_new_cdclk_state(state) \
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to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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int intel_cdclk_init(struct drm_i915_private *dev_priv);
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void intel_cdclk_debugfs_register(struct drm_i915_private *i915);
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#endif /* __INTEL_CDCLK_H__ */
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