0bfdd6da01
struct intel_dpll_hw_state has a spot for all possible PLL registers across all platforms (well, apart from cx0/snps). This makes it rather confusing when trying to figure out which members belong to which platform(s). Split the struct up into five different platform specific sub-structures. For now this will actually increase the size a little bit as we have to duplicate a few members from skl to icl, but that will be remedied soon when we turn the thing into a union. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240412182703.19916-17-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef _INTEL_DPLL_H_
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#define _INTEL_DPLL_H_
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#include <linux/types.h>
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struct dpll;
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_dpll_hw_state;
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enum pipe;
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void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
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int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
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u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
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void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
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struct intel_dpll_hw_state *dpll_hw_state);
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void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
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void chv_compute_dpll(struct intel_crtc_state *crtc_state);
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int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
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const struct dpll *dpll);
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void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
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void chv_enable_pll(const struct intel_crtc_state *crtc_state);
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void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
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void vlv_enable_pll(const struct intel_crtc_state *crtc_state);
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void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
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void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);
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void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
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struct dpll *best_clock);
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int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
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void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
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void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
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#endif
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