51e039542b
Allow intel_dsb_chain() to start the chained DSB at start of the undelaye vblank. This is slightly more involved than simply setting the bit as we must use the DEwake mechanism to eliminate pkgC latency. And DSB_ENABLE_DEWAKE itself is problematic in that it allows us to configure just a single scanline, and if the current scanline is already past that DSB_ENABLE_DEWAKE won't do anything, rendering the whole thing moot. The current workaround involves checking the pipe's current scanline with the CPU, and if it looks like we're about to miss the configured DEwake scanline we set DSB_FORCE_DEWAKE to immediately assert DEwake. This is somewhat racy since the hardware is making progress all the while we're checking it on the CPU. We can make things less racy by chaining two DSBs and handling the DSB_FORCE_DEWAKE stuff entirely without CPU involvement: 1. CPU starts the first DSB immediately 2. First DSB configures the second DSB, including its dewake_scanline 3. First DSB starts the second w/ DSB_WAIT_FOR_VBLANK 4. First DSB asserts DSB_FORCE_DEWAKE 5. First DSB waits until we're outside the dewake_scanline-vblank_start window 6. First DSB deasserts DSB_FORCE_DEWAKE That will guarantee that the we are fully awake when the second DSB starts to actually execute. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240624191032.27333-12-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna <animesh.manna@intel.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg_defs.h"
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_display;
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struct intel_dsb;
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enum pipe;
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enum intel_dsb_id {
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INTEL_DSB_0,
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INTEL_DSB_1,
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INTEL_DSB_2,
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I915_MAX_DSBS,
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};
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struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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enum intel_dsb_id dsb_id,
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unsigned int max_cmds);
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void intel_dsb_finish(struct intel_dsb *dsb);
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void intel_dsb_cleanup(struct intel_dsb *dsb);
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void intel_dsb_reg_write(struct intel_dsb *dsb,
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i915_reg_t reg, u32 val);
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void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
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i915_reg_t reg, u32 mask, u32 val);
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void intel_dsb_noop(struct intel_dsb *dsb, int count);
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void intel_dsb_nonpost_start(struct intel_dsb *dsb);
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void intel_dsb_nonpost_end(struct intel_dsb *dsb);
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void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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int lower, int upper);
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void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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int lower, int upper);
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void intel_dsb_chain(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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struct intel_dsb *chained_dsb,
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bool wait_for_vblank);
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void intel_dsb_commit(struct intel_dsb *dsb,
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bool wait_for_vblank);
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void intel_dsb_wait(struct intel_dsb *dsb);
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void intel_dsb_irq_handler(struct intel_display *display,
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enum pipe pipe, enum intel_dsb_id dsb_id);
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#endif
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