According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.
Fixes:
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.. | ||
dsi_phy.c | ||
dsi_phy.h | ||
dsi_phy_7nm.c | ||
dsi_phy_10nm.c | ||
dsi_phy_14nm.c | ||
dsi_phy_20nm.c | ||
dsi_phy_28nm.c | ||
dsi_phy_28nm_8960.c |