3034cc8107
There's only one instance of the pcode per tile, and for GT-related
accesses both the primary and media GT share the same register
interface. Since Xe was using per-GT locking, the pcode mutex wasn't
actually protecting everything that it should since concurrent accesses
related to a tile's primary GT and media GT were possible.
Fixes: dd08ebf6c3 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240829220619.789159-5-matthew.d.roper@intel.com
32 lines
963 B
C
32 lines
963 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_PCODE_H_
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#define _XE_PCODE_H_
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#include <linux/types.h>
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struct xe_tile;
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struct xe_device;
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void xe_pcode_init(struct xe_tile *tile);
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int xe_pcode_probe_early(struct xe_device *xe);
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int xe_pcode_ready(struct xe_device *xe, bool locked);
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int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
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u32 max_gt_freq);
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int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
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int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
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int timeout_ms);
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#define xe_pcode_write(tile, mbox, val) \
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xe_pcode_write_timeout(tile, mbox, val, 1)
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int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_ms);
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#define PCODE_MBOX(mbcmd, param1, param2)\
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(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
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| FIELD_PREP(PCODE_MB_PARAM1, param1)\
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| FIELD_PREP(PCODE_MB_PARAM2, param2))
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#endif
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