4a4027f25d
Supported priority value for input pins may differ with regard of NIC
firmware version. E810T NICs with 3.20/4.00 FW versions would accept
priority range 0-31, where firmware 4.10+ would support the range 0-9
and extra value of 255.
Remove the in-range check as the driver has no information on supported
values from the running firmware, let firmware decide if given value is
correct and return extack error if the value is not supported.
Fixes: d7999f5ea6 ("ice: implement dpll interface to control cgu")
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Tested-by: Sunitha Mekala <sunithax.d.mekala@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2022, Intel Corporation. */
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#ifndef _ICE_DPLL_H_
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#define _ICE_DPLL_H_
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#include "ice.h"
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#define ICE_DPLL_RCLK_NUM_MAX 4
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/** ice_dpll_pin - store info about pins
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* @pin: dpll pin structure
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* @pf: pointer to pf, which has registered the dpll_pin
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* @idx: ice pin private idx
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* @num_parents: hols number of parent pins
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* @parent_idx: hold indexes of parent pins
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* @flags: pin flags returned from HW
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* @state: state of a pin
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* @prop: pin properties
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* @freq: current frequency of a pin
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* @phase_adjust: current phase adjust value
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*/
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struct ice_dpll_pin {
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struct dpll_pin *pin;
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struct ice_pf *pf;
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u8 idx;
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u8 num_parents;
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u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];
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u8 flags[ICE_DPLL_RCLK_NUM_MAX];
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u8 state[ICE_DPLL_RCLK_NUM_MAX];
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struct dpll_pin_properties prop;
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u32 freq;
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s32 phase_adjust;
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};
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/** ice_dpll - store info required for DPLL control
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* @dpll: pointer to dpll dev
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* @pf: pointer to pf, which has registered the dpll_device
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* @dpll_idx: index of dpll on the NIC
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* @input_idx: currently selected input index
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* @prev_input_idx: previously selected input index
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* @ref_state: state of dpll reference signals
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* @eec_mode: eec_mode dpll is configured for
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* @phase_offset: phase offset of active pin vs dpll signal
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* @prev_phase_offset: previous phase offset of active pin vs dpll signal
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* @input_prio: priorities of each input
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* @dpll_state: current dpll sync state
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* @prev_dpll_state: last dpll sync state
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* @active_input: pointer to active input pin
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* @prev_input: pointer to previous active input pin
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*/
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struct ice_dpll {
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struct dpll_device *dpll;
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struct ice_pf *pf;
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u8 dpll_idx;
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u8 input_idx;
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u8 prev_input_idx;
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u8 ref_state;
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u8 eec_mode;
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s64 phase_offset;
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s64 prev_phase_offset;
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u8 *input_prio;
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enum dpll_lock_status dpll_state;
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enum dpll_lock_status prev_dpll_state;
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enum dpll_mode mode;
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struct dpll_pin *active_input;
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struct dpll_pin *prev_input;
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};
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/** ice_dplls - store info required for CCU (clock controlling unit)
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* @kworker: periodic worker
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* @work: periodic work
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* @lock: locks access to configuration of a dpll
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* @eec: pointer to EEC dpll dev
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* @pps: pointer to PPS dpll dev
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* @inputs: input pins pointer
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* @outputs: output pins pointer
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* @rclk: recovered pins pointer
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* @num_inputs: number of input pins available on dpll
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* @num_outputs: number of output pins available on dpll
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* @cgu_state_acq_err_num: number of errors returned during periodic work
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* @base_rclk_idx: idx of first pin used for clock revocery pins
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* @clock_id: clock_id of dplls
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* @input_phase_adj_max: max phase adjust value for an input pins
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* @output_phase_adj_max: max phase adjust value for an output pins
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*/
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struct ice_dplls {
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struct kthread_worker *kworker;
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struct kthread_delayed_work work;
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struct mutex lock;
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struct ice_dpll eec;
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struct ice_dpll pps;
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struct ice_dpll_pin *inputs;
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struct ice_dpll_pin *outputs;
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struct ice_dpll_pin rclk;
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u8 num_inputs;
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u8 num_outputs;
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int cgu_state_acq_err_num;
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u8 base_rclk_idx;
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u64 clock_id;
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s32 input_phase_adj_max;
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s32 output_phase_adj_max;
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};
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
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void ice_dpll_init(struct ice_pf *pf);
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void ice_dpll_deinit(struct ice_pf *pf);
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#else
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static inline void ice_dpll_init(struct ice_pf *pf) { }
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static inline void ice_dpll_deinit(struct ice_pf *pf) { }
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#endif
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#endif
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