109eb29172
It was observed that Tx performance was inconsistent across all queues
and/or VSIs and that it was directly connected to existing 9-layer
topology of the Tx scheduler.
Introduce new private devlink param - tx_scheduling_layers. This parameter
gives user flexibility to choose the 5-layer transmit scheduler topology
which helps to smooth out the transmit performance.
Allowed parameter values are 5 and 9.
Example usage:
Show:
devlink dev param show pci/0000:4b:00.0 name tx_scheduling_layers
pci/0000:4b:00.0:
name tx_scheduling_layers type driver-specific
values:
cmode permanent value 9
Set:
devlink dev param set pci/0000:4b:00.0 name tx_scheduling_layers value 5
cmode permanent
devlink dev param set pci/0000:4b:00.0 name tx_scheduling_layers value 9
cmode permanent
Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Co-developed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Signed-off-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
16 lines
575 B
C
16 lines
575 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018-2019, Intel Corporation. */
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#ifndef _ICE_FW_UPDATE_H_
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#define _ICE_FW_UPDATE_H_
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int ice_devlink_flash_update(struct devlink *devlink,
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struct devlink_flash_update_params *params,
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struct netlink_ext_ack *extack);
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int ice_get_pending_updates(struct ice_pf *pf, u8 *pending,
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struct netlink_ext_ack *extack);
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int ice_write_one_nvm_block(struct ice_pf *pf, u16 module, u32 offset,
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u16 block_size, u8 *block, bool last_cmd,
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u8 *reset_level, struct netlink_ext_ack *extack);
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#endif
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